Abstract: The present invention provides a carrier that provides improved retention to the individual contact elements resulting in LGA interposer connectors with improved manufacturability, reliability and more uniform mechanical and electrical performance. In one embodiment, the carrier, which includes upper and lower sections of dielectric material with an adhesive layer in between, includes a plurality of openings, each of which may contain an individual contact element. During assembly of the connector, once the contact elements are inserted, the adhesive layer is reflowed, thereby allowing the carrier to capture the location of the contact elements both with respect to each other as well as to the carrier. Alternately, the carrier may be implemented in a fashion that, while not including an adhesive layer to be reflowed, still provides improved retention of the individual contact elements. These embodiments may by easier to assemble, and less expensive to manufacture, especially in high volumes.

Abstract: The present invention features methods and apparatuses for sealing tiled, flat-panel displays (FPDs). Tile edges corresponding with the display's perimeter edges are designed with a wide seal. Interior edges, however, have narrow seals in order to maintain the desired, constant, pixel pitch across tile boundaries. In some cases, this invention applies specifically to arrays of tiles 2×2 or less, and, in other cases, to N×M arrays, where N and M are any integer numbers. The tiles are enclosed with top and bottom glass plates, which are sealed with an adhesive bond to the tiles on the outside perimeter of the tiled display. Vertical seams (where tiles meet at the perimeter of the FPD) are sealed with a small amount of polymer. The seal may be constructed between a cover plate and a back plate, sandwiching the tiles. The AMLCD edges may be coated with either a non-permeable material or a polymer having an extremely low permeability (for example, Parylene™).

Abstract: The present invention provides a carrier that provides improved retention to the individual contact elements resulting in LGA interposer connectors with improved manufacturability, reliability and more uniform mechanical and electrical performance. In one embodiment, the carrier, which includes upper and lower sections of dielectric material with an adhesive layer in between, includes a plurality of openings, each of which may contain an individual contact element. During assembly of the connector, once the contact elements are inserted, the adhesive layer is reflowed, thereby allowing the carrier to capture the location of the contact elements both with respect to each other as well as to the carrier. Alternately, the carrier may be implemented in a fashion that, while not including an adhesive layer to be reflowed, still provides improved retention of the individual contact elements. These embodiments may by easier to assemble, and less expensive to manufacture, especially in high volumes.

Abstract: An interposer for a land grid array includes a dielectric grid having an array of holes and a resilient, conductive button disposed in one or more of the holes. The button includes an insulating core, a conducting element wound around the insulating core, and an outer shell surrounding the conducting element. The characteristics of the conducting element and the buttons may be chosen such that the contact force and resistance, and compressibility or relaxability of the conductive buttons can be selected within wide limits. Contact areas between the shell and the conducting element urge a substantially corresponding displacement in both the conducting element and the shell when the button is under compression or relaxation. The interposer alternatively can include an insulating sheet and rather than conductive buttons contain conducting elements disposed therein having contact areas with the block.

Abstract: A large flat panel display having a plurality of tile display modules with capability in the range of 12 or more lines per inch, being precisely manufactured and aligned such that the interpixel spacing between two adjacent tiles maintains the uniformly periodic spacing of the interpixel spacing within tiles. The display is addressed as a single monolithic display, without reference to the plurality of individual tiles making up the display. All of the interconnections between tiles are located between tiles in the “shadow area”, unless all tiles can have an edge around the periphery of the display. Also disclosed are methods of making and assembling the tiles and the displays.

Abstract: A low insertion force connection using two interfitting components: a tapered element and a beam element which is deformed by the tapered element in the region where the primary forces are buckling, rather than bending. The present invention is based on pressure engaged insert/receptacle type of connections that are self-assembling, and require a minimized insertion force to produce a high and tunable contact force that is not applied through the component to be attached. Apart from differences in size, the same design principles are applicable from the chip level to the board level of a microelectronic system. The invention comprises a low cost pressure engaged electrical and thermal connection, based on insert/receptacle structures in which the contact force and insertion force are separated. Such a design allows tunable contact force while it minimizes the insertion force and allows also for self-assembly and reworkability.

Abstract: A large flat panel display having a plurality of tile display modules with capability in the range of 12 or more lines per inch, being precisely manufactured and aligned such that the interpixel spacing between two adjacent tiles maintains the uniformly periodic spacing of the interpixel spacing within tiles. The display is addressed as a single monolithic display, without reference to the plurality of individual tiles making up the display. All of the interconnections between tiles are located between tiles in the "shadow area", unless all tiles can have an edge around the periphery of the display. Also disclosed are methods of making and assembling the tiles and the displays.

Abstract: The present invention features methods and apparatuses for sealing tiled, flat-panel displays (FPDs). Tile edges corresponding with the display's perimeter edges are designed with a wide seal. Interior edges, however, have narrow seals in order to maintain the desired, constant, pixel pitch across tile boundaries. In some cases, this invention applies specifically to arrays of tiles 2.times.2 or less, and, in other cases, to N.times.M arrays, where N and M are any integer numbers. The tiles are enclosed with top and bottom glass plates, which are sealed with an adhesive bond to the tiles on the outside perimeter of the tiled display. Vertical seams (where tiles meet at the perimeter of the FPD) are sealed with a small amount of polymer. The seal may be constructed between a cover plate and a back plate, sandwiching the tiles. The AMLCD edges may be coated with either a non-permeable material or a polymer having an extremely low permeability (for example, Parylene.TM.).

Abstract: A panel display includes a common substrate on which a plurality of small display tiles are mounted in an array and electrically interconnected to replicate a large area panel. Each tile includes a plurality of contact pads which are aligned with corresponding contact pads on the substrate. Solder joints between corresponding contact pads mechanically align and secure the tiles on the substrate, and provide electrical connections therebetween. Selected substrate contact pads are electrically interconnected to provide electrical connections between adjacent tiles.

Abstract: The present invention features a tiled, substantially flat, panel display having the characteristic of visually imperceptible seams between the tiles for the intended viewing conditions, which include the perception thresholds of the human eye, the view distance, the display brightness and the level of the ambient light. The panel consists of an image source plane having spaced-apart pixels containing light-transmitting elements comprising single or multiple lightvalves. These lightvalves transmit monochromatic light, or primary color light spectra, for example, red, green and blue, in gray-scale and color displays, respectively. Each of the pixels is located along the image source plane at a uniform pitch greater than approximately 0.2 mm. Many adjacently-situated tiles are located in a plane in proximity to the image source plane. Secondary light rays can be controlled via light shields, aperture plates, masks and optical elements.

Abstract: A multiple layer interconnect structure for a semiconductor chip includes a graded transition layer of tungsten and a Group VIII metal, such as palladium, platinum or nickel (Pd, Pt or Ni) which allows formation of a Group VIII metal interconnect on a conventional pad of Al or Al alloy. The graded transition layer is interfaced between a thin adhesion layer on the pad and the Group VIII metal interconnect, and is approximately 100% tungsten where it interfaces the adhesion layer and approximately 100% Group VIII metal where it interfaces the interconnect layer. The tungsten in the graded transition layer acts as a solder barrier and the Group VIII metal interconnect is compatible with the silicon substrate so that packaging processing steps, including lead soldering, can be carried out, and the chip electrically tested, in the semiconductor fabrication facility.

Abstract: A panel display includes a common substrate on which a plurality of small display tiles are mounted in an array and electrically interconnected to replicate a large area panel. Each tile includes a plurality of contact pads which are aligned with corresponding contact pads on the substrate. Solder joints between corresponding contact pads mechanically align and secure the tiles on the substrate, and provide electrical connections therebetween. Selected substrate contact pads are electrically interconnected to provide electrical connections between adjacent tiles.

Abstract: Interconnect or metallization structures for integrated circuits on semiconductor chips contain blocked conductor segments to limit atomic transport from one segment to another thus minimizing stress migration and electromigration damage. Since the blocked conductor segments prevent atomic transport between two neighboring segments, the total amount of atoms and vacancies available for hillock and void growth in a segment can be controlled by the length of the segment. The conductor segments are made of high electrical conductance metals, such as aluminum, copper or gold based alloys, and are separated by very short segments of a high melting temperature refractory metal or alloy. Because of their high melting temperatures, refractory metals or alloys suppress atomic transport. The interconnect structures can be fabricated by conventional lithographic and deposition techniques.

Abstract: Interconnect structures for integrated circuits and semiconductor chips are disclosed which employ patterned interfaces to minimize stress migration in the interconnects. The interfaces are patterned to have regions of substantially no adhesion and other regions of good adhesion. The regions of substantially no adhesion reduce stress migration in the interconnect, while the regions of good adhesion ensure adequate thermal contact, fabricability and mechanical integrity of the interconnect structures. The patterned interfaces can be formed either by treating the surfaces of the interconnect or adjacent insulator and passivation layers, or by forming patterned interlayers of material in the interfaces. Multiple layer interconnects can also be formed which incorporate similarly patterned interfaces.