Abstract: Integrated circuit (IC) protections that prevent exposure or examination of integrated circuitry through backside analysis include a layer or mesh of an electrically conductive, electromagnetic radiation blocking material disposed over a backside of an IC device to prevent backside analysis. An electrically conductive conduit couples the material to a node of the integrated circuitry to provide a signal and/or voltage reference to the node through the layer/mesh. If the layer/mesh is tampered with, the integrated circuitry loses the voltage reference or signal thereby disabling the integrated circuitry. The IC device may include detection circuitry to monitor the node and to generate an alert and/or disable the circuitry upon tampering. The IC device may further include a support substrate, where a substrate between the material/mesh and the integrated circuitry is sufficiently thin that the IC device would be mechanically weak if the support substrate were removed.

Abstract: An integrated circuit (IC) device is disclosed which includes at least a first hybrid bond interface layer disposed between adjacent wafers of a wafer stack. Routing within the hybrid bond interface layer allows test pads exposed on a top wafer of the wafer stack to electrically couple test keys within the wafer stack. By utilizing the routing within the hybrid bond interface layer to index electrical connections between adjacent wafers, IC dies stacked on the wafers may be fabricated with less mask sets as compared to conventional designs.

Abstract: Methods for mitigating warpage on stacked wafers are provided herein. In one example, a method for mitigating warpage on stacked wafers includes depositing a first warpage compensating layer on a backside of a first wafer, stacking an active side of the first wafer on an active side of a second wafer to form a wafer stack having circuitry of the first wafer electrically connected to circuitry of the second wafer, and removing the first warpage compensating layer from the backside of the first wafer prior dicing the wafer stack.

Abstract: An integrated circuit (IC) device is disclosed which includes at least a first hybrid bond interface layer disposed between adjacent wafers of a wafer stack. Routing within the hybrid bond interface layer allows test pads exposed on a top wafer of the wafer stack to electrically couple test keys within the wafer stack. By utilizing the routing within the hybrid bond interface layer to index electrical connections between adjacent wafers, IC dies stacked on the wafers may be fabricated with less mask sets as compared to conventional designs.

Abstract: Circuits and methods involve an integrated circuit (IC) device, a plurality of application-specific sub-circuits, and a plurality of instances of a measuring circuit. The application-specific sub-circuits are disposed within respective areas of the IC device. Each instance of the measuring circuit is associated with one of the application-specific sub-circuits and is disposed within a respective one of the areas of the device. Each instance of the measuring circuit further includes a ring oscillator and a register for storage of a value indicative of an interval of time. Each instance of the measuring circuit is configured to measure passage of the interval of time based on a first clock signal, count oscillations of an output signal of the ring oscillator during the interval of time, and output a value indicating a number of oscillations counted during the interval of time.

Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of electrically floating extra-die heat transfer posts for improved thermal management. In one example, a chip package assembly is provided that includes a substrate, a first integrated circuit (IC) die, and a first plurality of electrically floating extra-die conductive posts. The substrate has a first surface and an opposing second surface. The first integrated circuit (IC) die has a first surface and an opposing second surface. The second surface of the first IC die is mounted to the first surface of the substrate. The first plurality of electrically floating extra-die conductive posts extend from the first surface of the first IC die to provide a heat transfer path away from the first IC die.

Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of extra-die heat transfer posts for improved thermal management. In one example, a chip package assembly is provided that includes a first integrated circuit (IC) die mounted to a substrate, a cover disposed over the first IC die, and a plurality of extra-die conductive posts disposed between the cover and substrate. The extra-die conductive posts provide a heat transfer path between the cover and substrate that is laterally outward of the first IC die.

Abstract: An integrated circuit device and techniques for manufacturing the same are described therein. The integrated circuit device leverages two or more pairs of stacked integrated circuit dies that are fabricated in mirror images to reduce the complexity of manufacturing, thus reducing cost. In one example, an integrated circuit device is provided that includes an integrated circuit (IC) die stack. The IC die stack includes first, second, third and fourth IC dies. The first and second IC dies are coupled by their active sides and include arrangements of integrated circuitry that are mirror images of each other. The third and fourth IC dies are also coupled by their active sides and include arrangements of integrated circuitry that are mirror images of each other.

Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of electrically floating heat transfer structures for improved thermal management. In one example, a chip package assembly is provided. The chip package assembly includes a substrate, a first integrated circuit (IC) die and a plurality of electrically floating conductive heat transfer structures. The substrate has a first surface and an opposing second surface. The first IC die has a first surface, an opposing second surface, and four lateral sides. The second surface of the first IC die is mounted to the first surface of the substrate. The plurality of electrically floating conductive heat transfer structures extend in a first direction defined between the first and second surfaces of the first IC die.

Abstract: Integrated circuit (IC) dies and method for manufacturing the same are described herein that mitigate pattern loading effects during manufacture. In one example, the IC includes a die body having a first circuit block separated from an adjacent second circuit block by a buffer zone. The first and second circuit blocks have first and second transistors that are at least partially fabricated from a gate metal layer and disposed immediately adjacent the buffer zone. A dummy structure is formed in the buffer zone and is also at least partially fabricated from the gate metal layer. An amount of gate metal layer material in the dummy structure is selected to mitigate differences in the amount of gate metal layer material in regions of first and second circuit blocks that neighbor each other across the buffer zone.

Abstract: An integrated circuit device and techniques for manufacturing the same are described therein. The integrated circuit device leverages two or more pairs of stacked integrated circuit dies that are fabricated in mirror images to reduce the complexity of manufacturing, thus reducing cost. In one example, an integrated circuit device is provided that includes an integrated circuit (IC) die stack. The IC die stack includes first, second, third and fourth IC dies. The first and second IC dies are coupled by their active sides and include arrangements of integrated circuitry that are mirror images of each other. The third and fourth IC dies are also coupled by their active sides and include arrangements of integrated circuitry that are mirror images of each other.

Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of electrically floating heat transfer structures for improved thermal management. In one example, a chip package assembly is provided. The chip package assembly includes a substrate, a first integrated circuit (IC) die and a plurality of electrically floating conductive heat transfer structures. The substrate has a first surface and an opposing second surface. The first IC die has a first surface, an opposing second surface, and four lateral sides. The second surface of the first IC die is mounted to the first surface of the substrate. The plurality of electrically floating conductive heat transfer structures extend in a first direction defined between the first and second surfaces of the first IC die.

Abstract: Device(s) and method(s) related generally to a wafer or die stack are disclosed. In one such device, a die stack of two or more integrated circuit dies has associated therewith test circuits corresponding to each level of the die stack each with a set of pads. A test data-input path includes being from: a test data-in pad through a test circuit to a test data-out pad of each of the test circuits; and the test data-out pad to the test data-in pad between consecutive levels of the test circuits. Each of the set of pads includes the test data-in pad and the test data-out pad respectively thereof. A test data-output path is coupled to the test data-out pad of a level of the levels.

Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of electrically floating extra-die heat transfer posts for improved thermal management. In one example, a chip package assembly is provided that includes a substrate, a first integrated circuit (IC) die, and a first plurality of electrically floating extra-die conductive posts. The substrate has a first surface and an opposing second surface. The first integrated circuit (IC) die has a first surface and an opposing second surface. The second surface of the first IC die is mounted to the first surface of the substrate. The first plurality of electrically floating extra-die conductive posts extend from the first surface of the first IC die to provide a heat transfer path away from the first IC die.

Abstract: An electronic device and method for fabricating the same are disclosed herein. In one example the electronic device includes a substrate, a first die stack, and a second die stack. The first die stack includes a first functional die and a first dummy die. The first functional die is mounted to the substrate. The second stack includes a plurality of serially stacked second functional dies mounted to the substrate. The first dummy die is stacked on the first functional die. The first dummy die has a top surface that is substantially coplanar with a top surface of the second die stack. In one particular example, the first die stack includes a logic die and the second die stack includes a plurality of serially stacked memory dies.

Abstract: An electronic device and method for fabricating the same are disclosed herein. In one example the electronic device includes a substrate, a first die stack, and a second die stack. The first die stack includes a first functional die and a first dummy die. The first functional die is mounted to the substrate. The second stack includes a plurality of serially stacked second functional dies mounted to the substrate. The first dummy die is stacked on the first functional die. The first dummy die has a top surface that is substantially coplanar with a top surface of the second die stack. In one particular example, the first die stack includes a logic die and the second die stack includes a plurality of serially stacked memory dies.

Abstract: A chip package assembly and method for fabricating the same are provided which utilize at least one modular core dice to reduce the cost of manufacture. The modular core dice include at least two die disposed on a wafer segment that are separated by a scribe lane. In one example, a chip package assembly is provided that includes an interconnect substrate stacked below a first wafer segment. The first wafer segment has a first die spaced from a second die by a first scribe lane. The interconnect substrate has conductive routing that is electrically connected to the first die and the second die through die connections.

Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of extra-die heat transfer posts for improved thermal management. In one example, a chip package assembly is provided that includes a first integrated circuit (IC) die mounted to a substrate, a cover disposed over the first IC die, and a plurality of extra-die conductive posts disposed between the cover and substrate. The extra-die conductive posts provide a heat transfer path between the cover and substrate that is laterally outward of the first IC die.

Abstract: A stacked wafer assembly and method for fabricating the same are described herein. In one example, a stacked wafer assembly includes a first wafer bonded to a second wafer. The first wafer includes a plurality of fully functional dies and a first partial die formed thereon. The second wafer includes a plurality of fully functional dies and a first partial die formed thereon. Bond pads formed over an inductor of the first partial die of the first wafer are bonded to bond pads formed on the first partial die of the second wafer to establish electrical connection therebetween.

Abstract: In an example implementation, an integrated circuit (IC) includes: a plurality of transistors disposed in a plurality of locations on a die of the IC; conductors coupled to terminals of each of the plurality of transistors; a digital-to-analog converter (DAC), coupled to the conductors, to drive voltage signals to the plurality of transistors in response to a digital input; and an analog-to-digital converter (ADC), coupled to at least a portion of the conductors, to generate samples in response to current signals induced in the plurality of transistors in response to the voltage signals, the samples being indicative of at least one electrostatic characteristic for the plurality of transistors.