Patents by Inventor Chee Hak Teh

Chee Hak Teh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210303491
    Abstract: Systems or methods of the present disclosure may provide high-bandwidth, low-latency connectivity for inter-die and/or intra-die communication of a modularized integrated circuit system. Such an integrated circuit system may include a first die of fabric circuitry sector(s), a second die of modular periphery intellectual property (IP), a passive silicon interposer coupling the first die to the second die, and a modular interface that includes a network-on-chip (NOC). The modular interface may provide high-bandwidth, low-latency communication between the first die and the second, between the fabric circuitry sector(s), and between the first die and a third die.
    Type: Application
    Filed: June 14, 2021
    Publication date: September 30, 2021
    Inventors: George Chong Hean Ooi, Lai Guan Tang, Chee Hak Teh
  • Patent number: 11093261
    Abstract: A method for dynamically configuring multiple processors based on needs of applications includes receiving, from an application, an acceleration request message including a task to be accelerated. The method further includes determining a type of the task and searching a database of available accelerators to dynamically select a first accelerator based on the type of the task. The method further includes sending the acceleration request message to a first acceleration interface located at a configurable processing circuit. The first acceleration interface sends the acceleration request message to a first accelerator, and the first accelerator accelerates the task upon receipt of the acceleration request message.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: August 17, 2021
    Assignee: Altera Corporation
    Inventors: Chee Hak Teh, Kenneth Chong Yin Tan
  • Patent number: 11080449
    Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: August 3, 2021
    Assignee: Intel Corporation
    Inventors: Chee Hak Teh, Ankireddy Nalamalpu, MD Altaf Hossain, Dheeraj Subbareddy, Sean R. Atsatt, Lai Guan Tang
  • Patent number: 11062070
    Abstract: Systems or methods of the present disclosure may facilitate meeting connectivity demands between the dies of the modularized integrated circuits. Such an integrated circuit system may include a first die of programmable fabric circuitry that is communicatively coupled to a second die of modular periphery intellectual property (IP) tile via a modular interface. The modular interface may enable communication between a first microbump of the first die and a second microbump of the second die using a time-division multiplexing (TDM) technique. The modular interface may also enable communication between the first microbump and the second microbump using a wire-to-wire connection that does not comprise the TDM technique.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: July 13, 2021
    Assignee: Intel Corporation
    Inventors: Lai Guan Tang, Chee Hak Teh
  • Patent number: 11036660
    Abstract: Systems or methods of the present disclosure may provide high-bandwidth, low-latency connectivity for inter-die and/or intra-die communication of a modularized integrated circuit system. Such an integrated circuit system may include a first die of fabric circuitry sector(s), a second die of modular periphery intellectual property (IP), a passive silicon interposer coupling the first die to the second die, and a modular interface that includes a network-on-chip (NOC). The modular interface may provide high-bandwidth, low-latency communication between the first die and the second, between the fabric circuitry sector(s), and between the first die and a third die.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: June 15, 2021
    Assignee: Intel Corporation
    Inventors: George Chong Hean Ooi, Lai Guan Tang, Chee Hak Teh
  • Publication number: 20210111116
    Abstract: The presently disclosed programmable fabric die includes a direct fabric die-to-fabric die interconnect interface column disposed in a sector of programmable logic fabric. Each row of the interconnect interface column includes at least one interconnect interface that is electrically coupled to a microbump. The microbump is configured to be electrically coupled to another microbump of another interconnect interface of another fabric die through an interposer. The fabric die may include multiple interconnect interface columns that each extend deep into the sector, enabling low latency connections between the fabric dies and reducing routing congestion. In some embodiments, the fabric die may include interconnect interfaces that are instead distributed throughout logic blocks of the sector.
    Type: Application
    Filed: December 22, 2020
    Publication date: April 15, 2021
    Inventors: Chee Hak Teh, Chee Seng Leong, Lai Guan Tang, Han Wooi Lim, Hee Kong Phoon
  • Publication number: 20210072908
    Abstract: A multichip package may include at least a main die mounted on a substrate. The main die may be coupled to one or more transceiver dies also mounted on the substrate. The main die may include one or more universal interface blocks configured to interface with an on-package memory device or an on-package expansion die, both of which can be mounted on the substrate. The expansion die may include external memory interface (EMIF) components for communicating with off-package memory devices and/or bulk random-access memory (RAM) components for storing large amounts of data for the main die. Smaller input-output blocks such as GPIO (general purpose input-output) or LVDS (low-voltage differential signaling) interfaces may be formed within the core fabric of the main die without causing routing congestion while providing the necessary clock source.
    Type: Application
    Filed: November 19, 2020
    Publication date: March 11, 2021
    Applicant: Intel Corporation
    Inventors: Chee Hak Teh, Curtis Wortman, Jeffrey Erik Schulz
  • Patent number: 10936511
    Abstract: Systems and methods for providing capability of access to distributed memory blocks using a global address scheme in a programmable logic device. Each of the distributed memory blocks includes routing circuitry that receives data, and in a first mode, decodes whether the data is intended for a respective distributed memory block. In a second mode, the data may bypass routing circuitry. Furthermore, the data may be received at the distributed memory block via cascade connections of distributed memory blocks in a column and/or via register in the programmable fabric of the programmable logic device.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: March 2, 2021
    Assignee: Intel Corporation
    Inventors: Sean R. Atsatt, Chee Hak Teh
  • Patent number: 10931283
    Abstract: An integrated circuit may include integrated memory that is formed from a chain of memory blocks. Each memory block may have configurable input and output circuits. The configurable input and output circuits may be interposed between memory circuitry such as a memory array from circuitry external to the memory circuitry. The configurable input and output circuits may have upstream and downstream memory block connection ports. In such a way, configurable input and output circuits in a first memory block may pass control and address signals and data to configurable input and output circuits in a second memory block. By using the configurable input and output circuits, the integrated memory in the integrated circuit may operate to accommodate large bandwidth flows without using the general routing fabric of the integrated circuit.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: February 23, 2021
    Assignee: Intel Corporation
    Inventors: Chang Kian Tan, Chee Hak Teh
  • Publication number: 20210011878
    Abstract: A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2× clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.
    Type: Application
    Filed: September 29, 2020
    Publication date: January 14, 2021
    Inventors: Chee Hak Teh, Arifur Rahman
  • Patent number: 10886218
    Abstract: The presently disclosed programmable fabric die includes a direct fabric die-to-fabric die interconnect interface column disposed in a sector of programmable logic fabric. Each row of the interconnect interface column includes at least one interconnect interface that is electrically coupled to a microbump. The microbump is configured to be electrically coupled to another microbump of another interconnect interface of another fabric die through an interposer. The fabric die may include multiple interconnect interface columns that each extend deep into the sector, enabling low latency connections between the fabric dies and reducing routing congestion. In some embodiments, the fabric die may include interconnect interfaces that are instead distributed throughout logic blocks of the sector.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Chee Hak Teh, Chee Seng Leong, Lai Guan Tang, Han Wooi Lim, Hee Kong Phoon
  • Patent number: 10871906
    Abstract: A multichip package may include at least a main die mounted on a substrate. The main die may be coupled to one or more transceiver dies also mounted on the substrate. The main die may include one or more universal interface blocks configured to interface with an on-package memory device or an on-package expansion die, both of which can be mounted on the substrate. The expansion die may include external memory interface (EMIF) components for communicating with off-package memory devices and/or bulk random-access memory (RAM) components for storing large amounts of data for the main die. Smaller input-output blocks such as GPIO (general purpose input-output) or LVDS (low-voltage differential signaling) interfaces may be formed within the core fabric of the main die without causing routing congestion while providing the necessary clock source.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: December 22, 2020
    Assignee: Intel Corporation
    Inventors: Chee Hak Teh, Curtis Wortman, Jeffrey Erik Schulz
  • Publication number: 20200226313
    Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.
    Type: Application
    Filed: March 27, 2020
    Publication date: July 16, 2020
    Inventors: Chee Hak Teh, Ankireddy Nalamalpu, MD Altaf Hossain, Dheeraj Subbareddy, Sean R. Atsatt, Lai Guan Tang
  • Publication number: 20200226094
    Abstract: A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2× clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.
    Type: Application
    Filed: March 27, 2020
    Publication date: July 16, 2020
    Inventors: Chee Hak Teh, Arifur Rahman
  • Patent number: 10714163
    Abstract: An integrated circuit is operable to communicate with an external component. The integrated circuit may include driver circuits for outputting clock signals and associated control signals to the external component in accordance with a predetermined interface protocol. The clock signals may toggle more frequently than the associated control signals. To help mitigate potential transistor aging effects that could negatively impact timing margins for the control signals, the control signals may be periodically toggled even during idle periods as allowed by the predetermined interface protocol to help improve timing margins.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: July 14, 2020
    Assignee: Intel Corporation
    Inventors: Tat Hin Tan, Chee Hak Teh, Tick Sern Loh, Wilfred Wee Kee King, Yu Ying Ong
  • Patent number: 10665548
    Abstract: An integrated circuit device or devices is presented that include internal connection ports to transmit data to or receive data from a first portion of the integrated circuit device. The integrated circuit device(s) also include external connection ports to transmit data to or receive data from outside the integrated circuit device, such as between integrated circuit devices. The integrated circuit device also includes remapping circuitry that remaps from a first connection between a first internal connection port of the internal connection ports and a first external connection port of the external connection ports to a second connection between a second internal connection port of the internal connection ports and a second external connection port of the external connection ports.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventor: Chee Hak Teh
  • Patent number: 10642946
    Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventors: Chee Hak Teh, Ankireddy Nalamalpu, Md Altaf Hossain, Dheeraj Subbareddy, Sean R. Atsatt, Lai Guan Tang
  • Publication number: 20200133902
    Abstract: Systems and method include one or more die coupled to an interposer. The interposer includes interconnection circuitry configured to electrically connect the one or more die together via the interposer. The interposer also includes translation circuitry configured to translate communications as they pass through the interposer. For instance, in the interposer, the translation circuitry translates communications, in the interposer, from a first protocol of a first die of the one or more die to a second protocol of a second die of the one or more die.
    Type: Application
    Filed: December 23, 2019
    Publication date: April 30, 2020
    Inventors: Lai Guan Tang, Ankireddy Nalamalpu, Dheeraj Subbareddy, Chee Hak Teh, MD Altaf Hossain
  • Publication number: 20200118606
    Abstract: Integrated circuits that include memory interface and controller circuitry for communicating with external memory are provided. The memory interface and controller circuitry may include a user logic interface, a memory controller, and a physical layer input-output interface. The user logic interface may be operated in a first clock domain. The memory controller may be operated in a second clock domain. The physical layer interface may be operated in a third clock domain that is an integer multiple of the second clock domain. The user logic interface may include only user-dependent blocks. The physical layer interface may include memory protocol agnostic blocks and/or memory protocol specific blocks. The memory controller may include both memory protocol agnostic blocks and memory protocol dependent blocks. The memory controller may include one or more color pipelines for scheduling memory requests in a parallel arbitration scheme.
    Type: Application
    Filed: November 14, 2019
    Publication date: April 16, 2020
    Inventor: Chee Hak Teh
  • Publication number: 20200104064
    Abstract: A multichip package may include at least a main die mounted on a substrate. The main die may be coupled to one or more transceiver dies also mounted on the substrate. The main die may include one or more universal interface blocks configured to interface with an on-package memory device or an on-package expansion die, both of which can be mounted on the substrate. The expansion die may include external memory interface (EMIF) components for communicating with off-package memory devices and/or bulk random-access memory (RAM) components for storing large amounts of data for the main die. Smaller input-output blocks such as GPIO (general purpose input-output) or LVDS (low-voltage differential signaling) interfaces may be formed within the core fabric of the main die without causing routing congestion while providing the necessary clock source.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Applicant: Intel Corporation
    Inventors: Chee Hak Teh, Curtis Wortman, Jeffrey Erik Schulz