Abstract: The present invention discloses a computer-implemented method of data transmission for a Network-on-Chip to allow high performance routing through dynamic allocated buffer. The method comprises the steps of transferring command or data in a form of plurality of flits from a source node to a router and further to a destination node, and transmitting the flits from the destination node back to the router, wherein the flits are packetized for transmission according to channel width and transaction width, sequence, and priority routing through physical and virtual channels.

Abstract: Described herein are memory controllers for integrated circuits that implement network-on-chip (NoC) to provide access to memory to couple processing cores of the integrated circuit to a memory device. The NoC may be dedicated to service the memory controller and may include one or more routers to facilitate management of the access to the memory controller.

Abstract: The present invention relates to a network-on-chip architecture (100), characterized by: a plurality of stampable partition (200), each partition including one or more router (10) adapted for communication, registers and pre-built communication links established in cardinal directions or other directions, and one or more configuration bus node (20) deposited in each partition (200) connecting to the registers (40); a system integrator connecting a system operator (60) to one of the configuration bus node (20); wherein the system operator (60) initializes a path mapping between the configuration bus node (20) forming a secondary configuration network and access the registers (40) in each partition to program the registers (40) with routing data A method of processing data at the network-on-chip architecture (100) is also disclosed herein.

Abstract: The presently disclosed programmable fabric die includes a direct fabric die-to-fabric die interconnect interface column disposed in a sector of programmable logic fabric. Each row of the interconnect interface column includes at least one interconnect interface that is electrically coupled to a microbump. The microbump is configured to be electrically coupled to another microbump of another interconnect interface of another fabric die through an interposer. The fabric die may include multiple interconnect interface columns that each extend deep into the sector, enabling low latency connections between the fabric dies and reducing routing congestion. In some embodiments, the fabric die may include interconnect interfaces that are instead distributed throughout logic blocks of the sector.

Abstract: A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2× clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.

Abstract: The present invention discloses a computer-implemented method for offset calibration and an integrated circuit (IC) memory controller for offset calibration. Said method comprises the step of: performing offset calibration of a receiver read-data strobe replica; conditioning pad voltages of a receiver read-data strobe and the receiver read-data strobe replica based on an offset calibration value of the receiver read-data strobe replica; and performing offset calibration of the receiver read-data strobe based on an offset calibration value of the pad voltages; wherein disabling differential inputs of transmission gate from a differential strobe signal pins to the receiver read-data strobe replica during receiver read-data strobe replica offset calibration.

Abstract: The present invention relates to a system (100 or 200) for aligning a programmable clock or strobe. The system (100 or 200) comprises a first programmable delay unit (1a) for receiving the programmable clock or strobe, characterized by a second programmable delay unit (1b) connected in parallel to the first programmable delay unit (1a) for receiving the programmable clock or strobe, a switch (2) for switching one of the two programmable delay units (1a or 1b) to service the programmable clock or strobe so as to allow the other programmable delay unit (1a or 1b) to adjust the other programmable clock or strobe, and a control logic component (3) for handling the switching of the switch (2), in which the switch (2) swaps in the adjusted programmable clock or strobe to service a downstream clocktree or strobe path after the programmable clock or strobe is adjusted. The present invention also relates to a method for aligning a programmable clock or strobe.

Abstract: The present invention relates to a system for network-on-chip power management. The system comprising a primary network-on-chip comprises multiple components, each component having a power controller, characterized by a secondary network-on-chip comprises a secondary network-on-chip master node and a plurality of secondary network-on-chip nodes connected thereto, the plurality of secondary network-on-chip nodes associated to the components of the primary network-on-chip for power managing individual and link components of the primary network-on-chip, and a power management unit connected to the secondary network-on-chip master node, configured to polling status registers of the components of the primary network-on-chip for accessing power states of each component, accessing routing information of the components of the primary network-on-chip and sending request to the secondary network-on-chip nodes for powering on or off the associated components of the primary network-chip through the power controller.

Abstract: The presently disclosed programmable fabric die includes a direct fabric die-to-fabric die interconnect interface column disposed in a sector of programmable logic fabric. Each row of the interconnect interface column includes at least one interconnect interface that is electrically coupled to a microbump. The microbump is configured to be electrically coupled to another microbump of another interconnect interface of another fabric die through an interposer. The fabric die may include multiple interconnect interface columns that each extend deep into the sector, enabling low latency connections between the fabric dies and reducing routing congestion. In some embodiments, the fabric die may include interconnect interfaces that are instead distributed throughout logic blocks of the sector.

Abstract: The present invention relates a network-on-chip (NoC) system for optimizing data transfer, the system comprising a plurality of nodes including a source node and a destination node; characterized by a plurality of routers attached to the plurality of nodes that route a plurality of data packets from the source node to the destination node; wherein each of the plurality of packets is tagged with a routing information (RINFO), each node is assigned with a node unique identifier (ID) and each router is assigned with a router unique identifier (RID) for each horizontal and vertical routing direction for 2D and 3D interconnect topologies; wherein each of the router comprising at least a pair of ingress port and egress port, a route decoder and an arbiter to support a synchronous, an asynchronous and a source-synchronous operations. The present invention also relates to a method of optimizing data transfer using the NoC system.

Abstract: The present invention relates to a computer-implemented method of generating a Network-on-Chip routing table, said method comprising the steps of: identifying source and destination by coordinates; sorting source-destination list based on user-input constraints; iterating source-destination pairs in the sorted source-destination list to find a shortest routing path from the source to the destination; splitting each source-destination pair to multiple sub source-destination pairs based on one of the user-input constraints; iterating each of the sub source-destination pairs to find a shortest routing path in a sub source-destination list; creating routing table for each sub source-destination pair based on the user-input constraints; combining the routing tables of sub source-destination pairs to generate a source-destination pairs routing table; performing routing table deadlock detection before proceeding to generate a routing table for next source-destination pair; wherein the user-input constraints comprisi

Abstract: The present invention discloses a computer-implemented method for offset calibration and an integrated circuit (IC) memory controller for offset calibration. Said method comprises the step of: performing offset calibration of a receiver read-data strobe replica; conditioning pad voltages of a receiver read-data strobe and the receiver read-data strobe replica based on an offset calibration value of the receiver read-data strobe replica; and performing offset calibration of the receiver read-data strobe based on an offset calibration value of the pad voltages; wherein disabling differential inputs of transmission gate from a differential strobe signal pins to the receiver read-data strobe replica during receiver read-data strobe replica offset calibration.

Abstract: The present invention relates to a system for network-on-chip power management. The system comprising a primary network-on-chip comprises multiple components, each component having a power controller, characterized by a secondary network-on-chip comprises a secondary network-on-chip master node and a plurality of secondary network-on-chip nodes connected thereto, the plurality of secondary network-on-chip nodes associated to the components of the primary network-on-chip for power managing individual and link components of the primary network-on-chip, and a power management unit connected to the secondary network-on-chip master node, configured to polling status registers of the components of the primary network-on-chip for accessing power states of each component, accessing routing information of the components of the primary network-on-chip and sending request to the secondary network-on-chip nodes for powering on or off the associated components of the primary network-chip through the power controller.

Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.

Abstract: Systems and methods described herein may relate to data transactions involving a microsector architecture. Control circuitry may organize transactions to and from the microsector architecture to, for example, enable direct addressing transactions as well as batch transactions across multiple microsectors. A data path disposed between programmable logic circuitry of a column of microsectors and a column of row controllers may form a micro-network-on-chip used by a network-on-chip to interface with the programmable logic circuitry.

Abstract: A memory controller for improving data integrity and providing data security. The memory controller including a transmit data path to transmit write data to a memory device, the transmit data path comprising a scrambling component, wherein the scrambling component includes a scrambling logic and an exclusive OR logic, wherein the write data is divided into a first portion and a second portion, wherein input of the scrambling logic comprises the first portion of the write data and an address associated with the write data to generate a pseudo-random output, and wherein input of the exclusive OR logic comprises the second portion of the write data, the pseudo-random output and a fixed seed corresponding to the first portion of the write data to generate a scrambled data.

Abstract: A method comprises the steps of receiving input from a user via user interface and selecting a plurality of flits from a plurality of ingress into a plurality of virtual channels followed by selecting the flits from the virtual channels into a plurality of egress based on the input from the user. The selection of the flits into the virtual channels and the egress characterized by the steps of computing default and elevated bandwidths of the virtual channels, computing default and elevated weights of the virtual channels based on the default and elevated bandwidths and generating a weightage lookup table using the default and elevated weights to perform arbitration weightage lookup for the flits with default and elevated priority levels for selecting the flits into the virtual channels and the egress, wherein the flits from the different ingress comprise different default and elevated weight.

Abstract: Systems and methods described herein may relate to data transactions involving a microsector architecture. Control circuitry may organize transactions to and from the microsector architecture to, for example, enable direct addressing transactions as well as batch transactions across multiple microsectors. A data path disposed between programmable logic circuitry of a column of microsectors and a column of row controllers may form a micro-network-on-chip used by a network-on-chip to interface with the programmable logic circuitry.

Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.

Abstract: The present invention relates to a system and method for transferring configuration, management, debug information and asynchronous events between network-on-chip (NOC) and external interface, wherein said system, referred to as secondary network (101), comprises of a plurality of configuration bus (CBUS) network elements such as a master network element (103) and a plurality of basic network elements (105); whereby said secondary network (101) is capable to convey events such as request, acknowledge assertions or de-assertions, saving the need for numerous wires connecting between main NOC elements such as nodes or routers.