Patents by Inventor Chee Hak Teh

Chee Hak Teh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250138623
    Abstract: The present invention relates to a system for network-on-chip power management. The system comprising a primary network-on-chip comprises multiple components, each component having a power controller, characterized by a secondary network-on-chip comprises a secondary network-on-chip master node and a plurality of secondary network-on-chip nodes connected thereto, the plurality of secondary network-on-chip nodes associated to the components of the primary network-on-chip for power managing individual and link components of the primary network-on-chip, and a power management unit connected to the secondary network-on-chip master node, configured to polling status registers of the components of the primary network-on-chip for accessing power states of each component, accessing routing information of the components of the primary network-on-chip and sending request to the secondary network-on-chip nodes for powering on or off the associated components of the primary network-chip through the power controller.
    Type: Application
    Filed: December 29, 2023
    Publication date: May 1, 2025
    Applicant: SKYECHIP SDN BHD
    Inventors: Chee Hak TEH, Yu Ying ONG, Soon Chieh LIM, MUHAMAD AIDIL BIN JAZMI, Yeong Tat LIEW, Weng Li LEOW
  • Publication number: 20250077753
    Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.
    Type: Application
    Filed: November 18, 2024
    Publication date: March 6, 2025
    Inventors: Chee Hak Teh, Ankireddy Nalamalpu, MD Altaf Hossain, Dheeraj Subbareddy, Sean R. Atsatt, Lai Guan Tang
  • Publication number: 20250036591
    Abstract: Systems and methods described herein may relate to data transactions involving a microsector architecture. Control circuitry may organize transactions to and from the microsector architecture to, for example, enable direct addressing transactions as well as batch transactions across multiple microsectors. A data path disposed between programmable logic circuitry of a column of microsectors and a column of row controllers may form a micro-network-on-chip used by a network-on-chip to interface with the programmable logic circuitry.
    Type: Application
    Filed: October 10, 2024
    Publication date: January 30, 2025
    Inventors: Ilya K. Ganusov, Ashish Gupta, Chee Hak Teh, Sean R. Atsatt, Scott Jeremy Weber, Parivallal Kannan, Aman Gupta, Gary Brian Wallichs
  • Patent number: 12210633
    Abstract: A memory controller for improving data integrity and providing data security. The memory controller including a transmit data path to transmit write data to a memory device, the transmit data path comprising a scrambling component, wherein the scrambling component includes a scrambling logic and an exclusive OR logic, wherein the write data is divided into a first portion and a second portion, wherein input of the scrambling logic comprises the first portion of the write data and an address associated with the write data to generate a pseudo-random output, and wherein input of the exclusive OR logic comprises the second portion of the write data, the pseudo-random output and a fixed seed corresponding to the first portion of the write data to generate a scrambled data.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: January 28, 2025
    Assignee: SKYECHIP SDN BHD
    Inventors: Yu Ying Ong, Muhamad Aidil Bin Jazmi, Soon Chieh Lim, Chee Hak Teh
  • Patent number: 12199884
    Abstract: A method comprises the steps of receiving input from a user via user interface and selecting a plurality of flits from a plurality of ingress into a plurality of virtual channels followed by selecting the flits from the virtual channels into a plurality of egress based on the input from the user. The selection of the flits into the virtual channels and the egress characterized by the steps of computing default and elevated bandwidths of the virtual channels, computing default and elevated weights of the virtual channels based on the default and elevated bandwidths and generating a weightage lookup table using the default and elevated weights to perform arbitration weightage lookup for the flits with default and elevated priority levels for selecting the flits into the virtual channels and the egress, wherein the flits from the different ingress comprise different default and elevated weight.
    Type: Grant
    Filed: December 13, 2022
    Date of Patent: January 14, 2025
    Assignee: SKYECHIP SDN BHD
    Inventors: Yeong Tat Liew, Yu Ying Ong, Soon Chieh Lim, Weng Li Leow, Chee Hak Teh
  • Patent number: 12164462
    Abstract: Systems and methods described herein may relate to data transactions involving a microsector architecture. Control circuitry may organize transactions to and from the microsector architecture to, for example, enable direct addressing transactions as well as batch transactions across multiple microsectors. A data path disposed between programmable logic circuitry of a column of microsectors and a column of row controllers may form a micro-network-on-chip used by a network-on-chip to interface with the programmable logic circuitry.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: December 10, 2024
    Assignee: ALTERA CORPORATION
    Inventors: Ilya K. Ganusov, Ashish Gupta, Chee Hak Teh, Sean R. Atsatt, Scott Jeremy Weber, Parivallal Kannan, Aman Gupta, Gary Brian Wallichs
  • Patent number: 12153866
    Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.
    Type: Grant
    Filed: May 31, 2023
    Date of Patent: November 26, 2024
    Assignee: Altera Corporation
    Inventors: Chee Hak Teh, Ankireddy Nalamalpu, MD Altaf Hossain, Dheeraj Subbareddy, Sean R. Atsatt, Lai Guan Tang
  • Patent number: 12149407
    Abstract: The present invention relates to a system and method for transferring configuration, management, debug information and asynchronous events between network-on-chip (NOC) and external interface, wherein said system, referred to as secondary network (101), comprises of a plurality of configuration bus (CBUS) network elements such as a master network element (103) and a plurality of basic network elements (105); whereby said secondary network (101) is capable to convey events such as request, acknowledge assertions or de-assertions, saving the need for numerous wires connecting between main NOC elements such as nodes or routers.
    Type: Grant
    Filed: December 7, 2022
    Date of Patent: November 19, 2024
    Assignee: SKYECHIP SDN BHD
    Inventors: Soon Chieh Lim, Chuen Heong Khuan, Chee Hak Teh
  • Patent number: 12125518
    Abstract: The present invention relates to a method and apparatus of calibrating memory interface, wherein said method and apparatus is able to periodically re-adjust the placement of the receive enable signal in order to have said receive enable signal to be in an optimum position in relation to the DQS signal from an external memory device to achieve maximum timing margin regardless of voltage or temperature drift and/or process aging to the integrated circuit.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: October 22, 2024
    Assignee: SkyeChip Sdn Bhd
    Inventors: Soon Chieh Lim, Hoong Chin Ng, Ching Liang Ooi, Chee Hak Teh
  • Publication number: 20240312909
    Abstract: The presently disclosed programmable fabric die includes a direct fabric die-to-fabric die interconnect interface column disposed in a sector of programmable logic fabric. Each row of the interconnect interface column includes at least one interconnect interface that is electrically coupled to a microbump. The microbump is configured to be electrically coupled to another microbump of another interconnect interface of another fabric die through an interposer. The fabric die may include multiple interconnect interface columns that each extend deep into the sector, enabling low latency connections between the fabric dies and reducing routing congestion. In some embodiments, the fabric die may include interconnect interfaces that are instead distributed throughout logic blocks of the sector.
    Type: Application
    Filed: May 21, 2024
    Publication date: September 19, 2024
    Inventors: Chee Hak Teh, Chee Seng Leong, Lai Guan Tang, Han Wooi Lim, Hee Kong Phoon
  • Publication number: 20240297846
    Abstract: The present invention discloses a computer-implemented method of data transmission for a Network-on-Chip to allow high performance routing through dynamic allocated buffer. The method comprises the steps of transferring command or data in a form of plurality of flits from a source node to a router and further to a destination node, and transmitting the flits from the destination node back to the router, wherein the flits are packetized for transmission according to channel width and transaction width, sequence, and priority routing through physical and virtual channels.
    Type: Application
    Filed: June 14, 2023
    Publication date: September 5, 2024
    Applicant: SKYECHIP SDN BHD
    Inventors: Chee Hak TEH, Yu Ying ONG, Soon Chieh LIM, Weng Li LEOW, Yeong Tat LIEW, Chuen Heong KHUAN, Manobindra GANDHI, Muhamad Aidil Bin JAZMI
  • Publication number: 20240296140
    Abstract: Described herein are memory controllers for integrated circuits that implement network-on-chip (NoC) to provide access to memory to couple processing cores of the integrated circuit to a memory device. The NoC may be dedicated to service the memory controller and may include one or more routers to facilitate management of the access to the memory controller.
    Type: Application
    Filed: May 13, 2024
    Publication date: September 5, 2024
    Inventors: Chee Hak Teh, Yu Ying Ong, George Chong Hean Ooi
  • Patent number: 12026008
    Abstract: An integrated circuit die includes input buffer circuits that are enabled during an input mode of operation in response to first control signals to transmit input signals into the integrated circuit die from conductive bumps. Each of the input buffer circuits is coupled to one of the conductive bumps. The integrated circuit die also includes output buffer circuits that are each coupled to one of the conductive bumps. The output buffer circuits are enabled during an output mode of operation in response to second control signals to transmit output signals from the integrated circuit die to the conductive bumps. The input buffer circuits are disabled from transmitting signals during the output mode of operation in response to the first control signals. The output buffer circuits are disabled from transmitting signals during the input mode of operation in response to the second control signals.
    Type: Grant
    Filed: October 25, 2022
    Date of Patent: July 2, 2024
    Assignee: Altera Corporation
    Inventors: Jeffrey Chromczak, Chooi Pei Lim, Lai Guan Tang, Chee Hak Teh, MD Altaf Hossain, Dheeraj Subbareddy, Ankireddy Nalamalpu
  • Publication number: 20240192721
    Abstract: The present invention relates to a system (100 or 200) for aligning a programmable clock or strobe. The system (100 or 200) comprises a first programmable delay unit (1a) for receiving the programmable clock or strobe, characterized by a second programmable delay unit (1b) connected in parallel to the first programmable delay unit (1a) for receiving the programmable clock or strobe, a switch (2) for switching one of the two programmable delay units (1a or 1b) to service the programmable clock or strobe so as to allow the other programmable delay unit (1a or 1b) to adjust the other programmable clock or strobe, and a control logic component (3) for handling the switching of the switch (2), in which the switch (2) swaps in the adjusted programmable clock or strobe to service a downstream clocktree or strobe path after the programmable clock or strobe is adjusted. The present invention also relates to a method for aligning a programmable clock or strobe.
    Type: Application
    Filed: February 17, 2023
    Publication date: June 13, 2024
    Applicant: SKYECHIP SDN BHD
    Inventors: TAT HIN TAN, SOON CHIEH LIM, ZHEN PENG CHOK, CHEE HAK TEH, CHEAU NIH TAN
  • Patent number: 12009298
    Abstract: The presently disclosed programmable fabric die includes a direct fabric die-to-fabric die interconnect interface column disposed in a sector of programmable logic fabric. Each row of the interconnect interface column includes at least one interconnect interface that is electrically coupled to a microbump. The microbump is configured to be electrically coupled to another microbump of another interconnect interface of another fabric die through an interposer. The fabric die may include multiple interconnect interface columns that each extend deep into the sector, enabling low latency connections between the fabric dies and reducing routing congestion. In some embodiments, the fabric die may include interconnect interfaces that are instead distributed throughout logic blocks of the sector.
    Type: Grant
    Filed: April 20, 2023
    Date of Patent: June 11, 2024
    Assignee: Intel Corporation
    Inventors: Chee Hak Teh, Chee Seng Leong, Lai Guan Tang, Han Wooi Lim, Hee Kong Phoon
  • Patent number: 11995028
    Abstract: Described herein are memory controllers for integrated circuits that implement network-on-chip (NoC) to provide access to memory to couple processing cores of the integrated circuit to a memory device. The NoC may be dedicated to service the memory controller and may include one or more routers to facilitate management of the access to the memory controller.
    Type: Grant
    Filed: December 27, 2022
    Date of Patent: May 28, 2024
    Assignee: Intel Corporation
    Inventors: Chee Hak Teh, Yu Ying Ong, George Chong Hean Ooi
  • Publication number: 20240163223
    Abstract: The present invention relates to a method (100) for network-on-chip arbitration. The method (100) comprises the steps of receiving input from a user via user interface and selecting a plurality of flits from a plurality of ingress into a plurality of virtual channels followed by selecting the flits from the virtual channels into a plurality of egress based on the input from the user. The selection of the flits into the virtual channels and the egress characterized by the steps of computing default and elevated bandwidths of the virtual channels, computing default and elevated weights of the virtual channels based on the default and elevated bandwidths and generating a weightage lookup table using the default and elevated weights to perform arbitration weightage lookup for the flits with default and elevated priority levels for selecting the flits into the virtual channels and the egress, wherein the flits from the different ingress comprise different default and elevated weight.
    Type: Application
    Filed: December 13, 2022
    Publication date: May 16, 2024
    Applicant: SKYECHIP SDN BHD
    Inventors: YEONG TAT LIEW, YU YING ONG, SOON CHIEH LIM, WENG LI LEOW, CHEE HAK TEH
  • Patent number: 11979152
    Abstract: An integrated circuit may include integrated memory that is formed from a chain of memory blocks. Each memory block may have configurable input and output circuits. The configurable input and output circuits may be interposed between memory circuitry such as a memory array from circuitry external to the memory circuitry. The configurable input and output circuits may have upstream and downstream memory block connection ports. In such a way, configurable input and output circuits in a first memory block may pass control and address signals and data to configurable input and output circuits in a second memory block. By using the configurable input and output circuits, the integrated memory in the integrated circuit may operate to accommodate large bandwidth flows without using the general routing fabric of the integrated circuit.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: May 7, 2024
    Assignee: Intel Corporation
    Inventors: Chang Kian Tan, Chee Hak Teh
  • Publication number: 20240129183
    Abstract: The present invention relates to a system and method for transferring configuration, management, debug information and asynchronous events between network-on-chip (NOC) and external interface, wherein said system, referred to as secondary network (101), comprises of a plurality of configuration bus (CBUS) network elements such as a master network element (103) and a plurality of basic network elements (105); whereby said secondary network (101) is capable to convey events such as request, acknowledge assertions or de-assertions, saving the need for numerous wires connecting between main NOC elements such as nodes or routers.
    Type: Application
    Filed: December 7, 2022
    Publication date: April 18, 2024
    Inventors: Soon Chieh LIM, Chuen Heong KHUAN, Chee Hak TEH
  • Publication number: 20240070039
    Abstract: The present invention relates to a method of debugging a targeted area or the whole network-on-chip (NOC) (101), whereby said targeted area or the whole NOC is triggered to enter into a freeze state before capturing of the state of the targeted area or the whole NOC (101) and unloading of the debug information, before finally said targeted area or the whole NOC is triggered to enter into an unfreeze state to allow forward progress to resume, using existing buffer storage, thus allowing user to debug and identify the source of issue without requiring a significant amount of extra storage.
    Type: Application
    Filed: October 7, 2022
    Publication date: February 29, 2024
    Inventors: Yu Ying ONG, Chee Hak TEH, Soon Chieh LIM, Weng Li LEOW, Muhamad Aidil BIN JAZMI, Yeong Tat LIEW