Abstract: Techniques for power tunnels on circuit boards are disclosed. A power tunnel may be created in a circuit board by drilling through non-conductive layers to a conductive trace and then filling in the hole with a conductor. A power tunnel can have a high cross-sectional area and can carry a larger amount of current than an equivalent-width trace, reducing the area on a circuit board required to carry that amount of current.

Abstract: An electronic device may include a chassis. The electronic device may include a first electronic component that may include a first substrate and a first interconnect. The electronic device may include a second electronic component that may include a second substrate and a second interconnect. The second substrate may be physically separated from the first substrate. An electrical trace may be coupled to the chassis of the electronic device. The electrical trace may be sized and shaped to interface with the first interconnect of the first electronic component. The electrical trace may be sized and shaped to interface with the second interconnect of the second electronic component. The first electronic component and the second electronic component may be in electrical communication through the electrical trace coupled to the chassis of the electronic device.

Abstract: Techniques for power tunnels on circuit boards are disclosed. A power tunnel may be created in a circuit board by drilling through non-conductive layers to a conductive trace and then filling in the hole with a conductor. A power tunnel can have a high cross-sectional area and can carry a larger amount of current than an equivalent-width trace, reducing the area on a circuit board required to carry that amount of current.

Abstract: Fan module interconnect apparatus are disclosed. An example fan module includes a fan and a fan housing to carry the fan. The fan is to rotate in the fan housing. A flange extends from the fan housing and including signal paths to provide an interconnect to electrically couple at least portions of a first electrical circuit and a second electrical circuit of an electronic device.

Abstract: An electronic device may include a chassis. The electronic device may include a first electronic component that may include a first substrate and a first interconnect. The electronic device may include a second electronic component that may include a second substrate and a second interconnect. The second substrate may be physically separated from the first substrate. An electrical trace may be coupled to the chassis of the electronic device. The electrical trace may be sized and shaped to interface with the first interconnect of the first electronic component. The electrical trace may be sized and shaped to interface with the second interconnect of the second electronic component. The first electronic component and the second electronic component may be in electrical communication through the electrical trace coupled to the chassis of the electronic device.

Abstract: Embodiments of the invention may include a reference input port to receive a reference clock, the reference clock being based on a bypass clock, a feedback input port to receive a feedback clock from a clocked circuit, and logic to compare the reference clock and the feedback clock and to generate an output based on the comparison.

Abstract: A system is provided that includes a phase lock loop component to output a first signal based on a reference clock signal and a feedback clock signal. A clock distribution network may distribute a clock signal based on the first signal output from the phase lock loop component. Additionally, a delay lock loop component may deskew a signal and adjust the clock signal distributed by the clock distribution network.

Abstract: A method transfers a signal from a transmitting device to a receiving device. The signal is output from the transmitting device using a driving circuit. A reference clock signal is received in the transmitting device. An output clock signal is generated according to the received reference clock signal and a feedback clock signal in a phase locked loop. A delay is provided in a path of the reference clock signal and a path of the feedback clock signal. The delay is configured to make the output signal meet a predetermined valid data timing requirement.

Abstract: A multi-loop circuit includes a first switching device to receive a first clock pulse and a second delayed pulse and produce a first output pulse including either the first clock pulse or the second delayed pulse. A first delay device receives the first output pulse and produces a first delayed pulse. A second switching device receives a second clock pulse and the first delayed pulse and produces a second output pulse including either the second clock pulse or the first delayed pulse. A second delay device receives the second output pulse and produces the second delayed pulse. A third switching device receives the first and second delayed pulses and produces a first output signal. A fourth switching device receives the first and second delayed pulses and produces a second output signal. A controller is coupled to control the first, second, third, and fourth switching devices.

Abstract: A processor having asymmetric secondary processing resources. One disclosed embodiment includes a first execution resource to perform a first function and a second execution resource that also performs the second function, although the second processing resource is asymmetric to the first resource in that it has a lower throughput than the first processing resource. Switching logic switches execution from the first processing resource to the second processing resource in a reduced power consumption mode.

Abstract: A method and apparatus for jitter reduction in a Phase Locked Loop (PLL) that includes determining a size of a original charge pump adequate to generate an appropriate control voltage to a Voltage Controlled Oscillator (VCO) of a PLL based on the charge pump receiving a single up signal or down signal within one cycle of a PLL input reference clock. N number of the up signal or down signal are generated to a second charge pump 1/N the size of the original charge pump. The N number of the up signal or the down signal occurs within one cycle of the PLL input reference clock. The second charge pump generates N second control voltage corrections each being 1/N the amplitude of the appropriate control voltage glitch, thus minimizing glitches on the second control voltages and reducing jitter to the VCO.

Abstract: A phase-locked loop includes a phase detector to measure a phase offset between a reference clock signal and a feedback clock signal, and to generate first and second output control signals having a pulse width corresponding to the phase offset. The phase locked loop further includes a first pulse width control circuit coupled to the phase detector to reduce the pulse width of the first output control signal producing a first modified output control signal, a second pulse width control circuit coupled to the phase detector to reduce the pulse width of the second output control signal producing a second modified output control signal, a first charge pump coupled to the phase detector to provide a first charge signal responsive to the first and second output control signals, and a second charge pump coupled to the first and second pulse width control circuits to provide a second charge signal responsive to the first and second modified output control signals.

Abstract: An apparatus and method are provided for operating a processor core. This may include a first circuit to operate at a frequency that is dependent on a power supply voltage. A frequency control circuit may be provided to control a frequency of the first circuit by directing a voltage regulator to increase or decrease the power supply voltage.

Abstract: A self-biased phase locked loop (PLL) circuit includes a charge pump to generate a control voltage, a controlled oscillator coupled to the charge pump to generate the output signal based at least in part upon the control voltage, discharge circuitry coupled to the charge pump to discharge the control voltage, and frequency detection circuitry coupled to the controlled oscillator and the discharge circuitry to generate a digital feedback signal for terminating discharge of the control voltage by the discharge circuitry when the output signal reaches a threshold frequency that is a fraction of the target frequency.

Abstract: A method and apparatus for generating clock frequencies using cascaded phase-locked loop (PLL) circuits includes a first PLL circuit coupled to a second PLL circuit to produce a microprocessor I/O data clock signal and a microprocessor core clock signal, respectively. In one embodiment, the first PLL produces the data clock signal based upon a first reference signal and a first feedback signal, where the first feedback signal is derived from the data clock signal. Furthermore, the second PLL circuit produces the core clock signal based at least in part upon a second reference signal and a second feedback signal, where the second reference signal is derived from the data clock signal and the second feedback signal is derived from the core clock signal.

Abstract: A method and apparatus for generating clock frequencies using cascaded phase-locked loop (PLL) circuits includes a first PLL circuit coupled to a second PLL circuit to produce a microprocessor I/O data clock signal and a microprocessor core clock signal, respectively. In one embodiment, the first PLL produces the data clock signal based upon a first reference signal and a first feedback signal, where the first feedback signal is derived from the data clock signal. Furthermore, the second PLL circuit produces the core clock signal based at least in part upon a second reference signal and a second feedback signal, where the second reference signal is derived from the data clock signal and the second feedback signal is derived from the core clock signal.

Abstract: A phase-locked loop includes a phase detector to measure a phase offset between a reference clock signal and a feedback clock signal, and to generate first and second output control signals having a pulse width corresponding to the phase offset. The phase locked loop further includes a first pulse width control circuit coupled to the phase detector to reduce the pulse width of the first output control signal producing a first modified output control signal, a second pulse width control circuit coupled to the phase detector to reduce the pulse width of the second output control signal producing a second modified output control signal, a first charge pump coupled to the phase detector to provide a first charge signal responsive to the first and second output control signals, and a second charge pump coupled to the first and second pulse width control circuits to provide a second charge signal responsive to the first and second modified output control signals.

Abstract: A system is provided that includes a phase lock loop component to output a first signal based on a reference clock signal and a feedback clock signal. A clock distribution network may distribute a clock signal based on the first signal output from the phase lock loop component. Additionally, a delay lock loop component may deskew a signal and adjust the clock signal distributed by the clock distribution network.

Abstract: An apparatus and method are provided for operating a processor core. This may include a first circuit to operate at a frequency that is dependent on a power supply voltage. A frequency control circuit may be provided to control a frequency of the first circuit by directing a voltage regulator to increase or decrease the power supply voltage.

Abstract: A clock generating circuit is provided that includes a plurality of distributed ring oscillators to drive a clock distribution network. Multiplexing devices may select a length or delay of each of the ring oscillators. The variable length or delay may thereby adjust the frequency of the clock generating circuit.