Patents by Inventor Chee How Lim

Chee How Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6424170
    Abstract: A pull-up circuit has substantially linear current-voltage (I-V) characteristics for use in a bus system, such as in an open drain bus architecture type system. Operation in the linear region of the I-V characteristics is useful in high frequency input/output circuits. The pull-up circuit includes a transistor and a single termination resistor coupled to the transistor, and is simpler than other types of pull-up circuits. This simplicity in design saves area on a chip. The termination resistor in the pull-up circuit can be an n-well resistor formed on the same chip as the transistor, thereby further contributing to the savings in chip area.
    Type: Grant
    Filed: May 18, 2001
    Date of Patent: July 23, 2002
    Assignee: Intel Corporation
    Inventors: Raghu P. Raman, Songmin Kim, Chee How Lim, Usman A. Mughal
  • Patent number: 6411122
    Abstract: In a system, such as an open-drain bus architecture system, a termination impedance can be dynamically coupled or de-coupled from a bus. The termination impedance is coupled to the bus by a dynamic control circuit if a signal is being received from the bus or if a binary 1 is driven on the bus. The termination impedance is de-coupled from the bus by the dynamic control circuit if a binary 0 is driven on the bus. Coupling the termination impedance to the bus improves signal quality by providing a matching impedance. De-coupling the termination impedance reduces power dissipation and improves receiver noise margin.
    Type: Grant
    Filed: October 27, 2000
    Date of Patent: June 25, 2002
    Assignee: Intel Corporation
    Inventors: Usman A. Mughal, Razi Uddin, Chee How Lim, Songmin Kim, Steve Peterson, Raghu P. Raman
  • Patent number: 6351136
    Abstract: A circuit for providing protection to active termination devices and drive circuits from overshoot and undershoot noise is disclosed. The circuit includes an interconnect node, an active termination device, a drive circuit, and a voltage limiter for controlling noise overshoot and undershoot at the interconnect node. The voltage limiter controls the impedance at the interconnect node and the voltage swing at the interconnect node. Controlling the impedance reduces the overshoot and undershoot noise at the interconnect node. Controlling the voltage swing reduces the voltage swings across the transistors in the active termination devices and the drive circuits, which reduces the effects of overshoot and undershoot noise on the active termination devices and the drive circuits. The result is less stress on the oxide layers in the transistors and an increased transistor lifetime.
    Type: Grant
    Filed: December 8, 1999
    Date of Patent: February 26, 2002
    Assignee: Intel Corporation
    Inventors: Jeff R. Jones, Chee How Lim
  • Patent number: 6157206
    Abstract: Integrated circuits include an impedance control circuit having at least one output terminal coupled to an on-chip reference termination device in order to control output impedance of the reference termination device such that it matches that of an external resistance. The impedance control circuit outputs are also coupled to the on-chip impedance-controlled termination devices which are coupled to each of the external transmission lines to be terminated. In this way, a single reference resistance allows many transmission lines to be properly terminated. The impedance-controlled termination devices are may be implemented as pairs of binary weighted p-channel and n-channel field effect transistors.
    Type: Grant
    Filed: December 31, 1998
    Date of Patent: December 5, 2000
    Assignee: Intel Corporation
    Inventors: Gregory F. Taylor, Jack A. Price, Chee How Lim