Patents by Inventor Chee Kian Ong
Chee Kian Ong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160329306Abstract: A semiconductor package and a manufacturing method thereof are provided. The package element has a first insulating layer, and a plurality of holes are disposed on the first surface of the first insulating layer. Besides, a plurality of package traces are embedded in the insulating layer and connected to the other end of the holes. The holes function as a positioning setting for connecting the solder balls to the package traces, such that the signal of the semiconductor chip is connected to the package trace via conductor of the chip, and further transmitted externally via solder ball. The elastic modulus of the material of the first insulating layer is preferably larger than 1.0 GPa.Type: ApplicationFiled: July 18, 2016Publication date: November 10, 2016Applicant: ADVANPACK SOLUTIONS PTE LTD.Inventors: Hwee-Seng Jimmy CHEW, Chee-Kian ONG, Bin Chichik ABD. RAZAK
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Publication number: 20160268225Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has an active surface. The semiconductor device includes at least a connecting element and at least a bump. The connecting element is disposed on the activate surface and has a minimum dimension smaller than 100 microns. The bump is disposed on the connecting element and is electrically connected to the active surface by the connecting element. The bump includes a pillar part disposed on the connecting element and a top part disposed at the top of the pillar part. The pillar part has a first dimension and a second dimension both parallel to the active surface. The first dimension is longer than 1.2 times the second dimension. The top part is composed of solder and will melt under the determined temperature. The pillar part will not melt under a determined temperature.Type: ApplicationFiled: May 18, 2016Publication date: September 15, 2016Applicant: ADVANPACK SOLUTIONS PTE LTD.Inventors: Hwee-Seng Jimmy CHEW, Chee-Kian ONG
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Patent number: 9396982Abstract: A semiconductor package and a manufacturing method thereof are provided. The package element has a first insulating layer, and a plurality of holes are disposed on the first surface of the first insulating layer. Besides, a plurality of package traces are embedded in the insulating layer and connected to the other end of the holes. The holes function as a positioning setting for connecting the solder balls to the package traces, such that the signal of the semiconductor chip is connected to the package trace via conductor of the chip, and further transmitted externally via solder ball. The elastic modulus of the material of the first insulating layer is preferably larger than 1.0 GPa.Type: GrantFiled: November 26, 2008Date of Patent: July 19, 2016Assignee: ADVANPACK SOLUTIONS PTE LTD.Inventors: Hwee-Seng Jimmy Chew, Chee Kian Ong, Bin Chichik Abd. Razak
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Patent number: 9362206Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has an active surface. The semiconductor device includes at least a connecting element and at least a bump. The connecting element is disposed on the activate surface and has a minimum dimension smaller than 100 microns. The bump is disposed on the connecting element and is electrically connected to the active surface by the connecting element. The bump includes a pillar part disposed on the connecting element and a top part disposed at the top of the pillar part. The pillar part has a first dimension and a second dimension both parallel to the active surface. The first dimension is longer than 1.2 times the second dimension. The top part is composed of solder and will melt under the determined temperature. The pillar part will not melt under a determined temperature.Type: GrantFiled: June 23, 2014Date of Patent: June 7, 2016Assignee: ADVANPACK SOLUTIONS PTE LTD.Inventors: Hwee-Seng Jimmy Chew, Chee-Kian Ong
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Patent number: 9287157Abstract: A semiconductor element that includes a forsy patterned conductive layer, a second pattern conductive layer and an insulating layer. The first surface of the second patterned conductive layer is connected to a second surface of the first patterned conductive layer. The insulating layer includes at least one space on a second surface thereof. The first patterned conductive layer and the second patterned conductive layer are embedded in the insulating layer between a first surface and a second surface thereof, the first surface of the first patterned conductive layer is entirely exposed on a first surface of the insulating layer, a second surface of the second patterned conductive layer is entirely exposed on the second surface of the insulating layer, and the space exposes the second surface of the first patterned conductive layer.Type: GrantFiled: June 29, 2010Date of Patent: March 15, 2016Assignee: ADVANPACK SOLUTIONS PTE LTD.Inventors: Hwee-Seng Jimmy Chew, Chee Kian Ong, Bin Chichik Abd. Razak
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Patent number: 9120169Abstract: A method for fabricating a flip-chip semiconductor package. The method comprises processing a semiconductor device, for example a semiconductor chip and processing a device carrier, for example a substrate. The semiconductor device comprises bump structures formed on a surface thereof. The substrate comprises bond pads formed on a surface thereof. Processing of the semiconductor chip results in heating of the semiconductor chip to a chip process temperature. The chip process temperature melts solder portions on the bump structures Processing of the substrate results in heating of the substrate to a substrate process temperature. The method comprises spatially aligning the semiconductor chip in relation to the substrate to correspondingly align the bump structures in relation to the bump pads. The semiconductor chip is then displaced towards the substrate for abutting the bump structures of the semiconductor chip with the bond pads of the substrate to thereby form bonds therebetween.Type: GrantFiled: November 9, 2009Date of Patent: September 1, 2015Assignee: ORION SYSTEMS INTEGRATION PTE LTDInventors: Hwee Seng Chew, Chee Kian Ong, Kian Hock Lim, Amlan Sen, Shoa Siong Lim
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Publication number: 20140299984Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has an active surface. The semiconductor device includes at least a connecting element and at least a bump. The connecting element is disposed on the activate surface and has a minimum dimension smaller than 100 microns. The bump is disposed on the connecting element and is electrically connected to the active surface by the connecting element. The bump includes a pillar part disposed on the connecting element and a top part disposed at the top of the pillar part. The pillar part has a first dimension and a second dimension both parallel to the active surface. The first dimension is longer than 1.2 times the second dimension. The top part is composed of solder and will melt under the determined temperature. The pillar part will not melt under a determined temperature.Type: ApplicationFiled: June 23, 2014Publication date: October 9, 2014Applicant: ADVANPACK SOLUTIONS PTE LTD.Inventors: Hwee-Seng Jimmy Chew, Chee-Kian ONG
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Patent number: 8846519Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has an active surface. The semiconductor device includes at least a connecting element and at least a bump. The connecting element is disposed on the activate surface and has a minimum dimension smaller than 100 microns. The bump is disposed on the connecting element and is electrically connected to the active surface by the connecting element. The bump includes a pillar part disposed on the connecting element and a top part disposed on the top of the pillar part. The pillar part has a first dimension and a second dimension both parallel to the active surface. The first dimension is more than 1.2 times the second dimension. The top part is composed of solder and will melt under a pre-determined temperature. The pillar part will not melt under the pre-determined temperature.Type: GrantFiled: May 9, 2012Date of Patent: September 30, 2014Assignee: Advanpack Solutions Pte Ltd.Inventors: Hwee-Seng Jimmy Chew, Chee Kian Ong
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Patent number: 8796844Abstract: A package structure including a first semiconductor element, a second semiconductor element, a semiconductor interposer and a substrate is provided. The first semiconductor element includes multiple first conductive bumps. The second semiconductor element includes multiple second conductive bumps. The semiconductor interposer includes a connection motherboard, at least one signal wire and at least one signal conductive column. The signal wire is disposed on the connection motherboard. The two ends of the signal wire are electrically connected to one of the first conductive bumps and one of the second conductive bumps respectively. The signal conductive column is electrically connected to the signal wire. The substrate is electrically connected to the signal conductive column. The first and the second semiconductor elements have the same circuit structure. The substrate of the package structure can simultaneously form a signal communication path with the first and the second semiconductor element respectively.Type: GrantFiled: September 2, 2009Date of Patent: August 5, 2014Assignee: AdvanPack Solutions Pte Ltd.Inventors: Hwee-Seng Jimmy Chew, Chee Kian Ong
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Patent number: 8766438Abstract: The invention discloses a package structure including a semiconductor device, a first protection layer, a second protection layer and at least one conductive connector. The semiconductor device has at least one pad. The first protection layer is disposed on the semiconductor device and exposes the pad. The second protection layer, disposed on the first protection layer, has at least one first opening and at least one second opening. The first opening exposes a partial surface of the pad. The second opening exposes a partial surface of the first protection layer. The conductive connector, opposite to the pad, is disposed on the second protection layer and coupled to the pad through the first openings.Type: GrantFiled: September 1, 2009Date of Patent: July 1, 2014Assignee: Advanpack Solutions PTE Ltd.Inventors: Hwee-Seng Jimmy Chew, Chee Kian Ong, Kee Kwang Lau
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Publication number: 20120220118Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has an active surface. The semiconductor device includes at least a connecting element and at least a bump. The connecting element is disposed on the activate surface and has a minimum dimension smaller than 100 microns. The bump is disposed on the connecting element and is electrically connected to the active surface by the connecting element. The bump includes a pillar part disposed on the connecting element and a top part disposed at the top of the pillar part. The pillar part has a first dimension and a second dimension both parallel to the active surface. The first dimension is longer than 1.2 times the second dimension. The top part is composed of solder and will melt under the determined temperature. The pillar part will not melt under a determined temperature.Type: ApplicationFiled: May 9, 2012Publication date: August 30, 2012Applicant: ADVANPACK SOLUTIONS PTE LTD.Inventors: Hwee-Seng Jimmy CHEW, Chee Kian ONG
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Patent number: 8207608Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has an active surface. The semiconductor device includes at least a connecting element and at least a bump. The connecting element is disposed on the activate surface and has a minimum dimension smaller than 100 microns. The bump is disposed on the connecting element and is electrically connected to the active surface by the connecting element. The bump includes a pillar part disposed on the connecting element and a top part disposed on the top of the pillar part. The pillar part has a first dimension and a second dimension both parallel to the active surface. The first dimension is longer than 1.2 times the second dimension. The top part is composed of solder and will melt under a pre-determined temperature. The pillar part will not melt under the pre-determined temperature.Type: GrantFiled: October 1, 2007Date of Patent: June 26, 2012Assignee: Advanpack Solutions Pte Ltd.Inventors: Hwee-Seng Jimmy Chew, Chee Kian Ong
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Publication number: 20120153466Abstract: A package structure including a first semiconductor element, a second semiconductor element, a semiconductor interposer and a substrate is provided. The first semiconductor element includes multiple first conductive bumps. The second semiconductor element includes multiple second conductive bumps. The semiconductor interposer includes a connection motherboard, at least one signal wire and at least one signal conductive column. The signal wire is disposed on the connection motherboard. The two ends of the signal wire are electrically connected to one of the first conductive bumps and one of the second conductive bumps respectively. The signal conductive column is electrically connected to the signal wire. The substrate is electrically connected to the signal conductive column. The first and the second semiconductor elements have the same circuit structure. The substrate of the package structure can simultaneously form a signal communication path with the first and the second semiconductor element respectively.Type: ApplicationFiled: September 2, 2009Publication date: June 21, 2012Inventors: Hwee-Seng Jimmy Chew, Chee Kian Ong
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Publication number: 20110287560Abstract: A method for fabricating a flip-chip semiconductor package. The method comprises processing a semiconductor device, for example a semiconductor chip and processing a device carrier, for example a substrate. The semiconductor device comprises bump structures formed on a surface thereof. The substrate comprises bond pads formed on a surface thereof. Processing of the semiconductor chip results in heating of the semiconductor chip to a chip process temperature. The chip process temperature melts solder portions on the bump structures Processing of the substrate results in heating of the substrate to a substrate process temperature. The method comprises spatially aligning the semiconductor chip in relation to the substrate to correspondingly align the bump structures in relation to the bump pads. The semiconductor chip is then displaced towards the substrate for abutting the bump structures of the semiconductor chip with the bond pads of the substrate to thereby form bonds therebetween.Type: ApplicationFiled: November 9, 2009Publication date: November 24, 2011Applicant: ORION SYSTEMS INTEGRATION PTE LTDInventors: Hwee Seng Chew, Chee Kian Ong, Kian Hock Lim, Amlan Sen, Shoa Siong Lim
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Publication number: 20080248610Abstract: The present invention provides a thermal bonding process for chip packaging. In accordance with an aspect of the invention, there is provided an approach to solve the problems caused by the different CTEs between the die and the substrate. It discloses an improved thermal bonding process for forming pillar-shaped interconnection, which controls the thermal expansion of the semiconductor die and the substrate by applying differential heating temperature to the two, thereby minimizing the misalignment between the die and the substrate, overcoming the stresses imposed on the interconnection and allowing more reliable and accurate packaging.Type: ApplicationFiled: April 3, 2007Publication date: October 9, 2008Applicant: Advanpack Solutions Pte LtdInventors: Hwee Seng Chew, Chee Kian Ong, Balasubramanian Sivagnanam
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Publication number: 20080145967Abstract: A semiconductor package and a manufacturing method thereof are provided. The package element has a first insulating layer, and a plurality of holes are disposed on the first surface of the first insulating layer. Besides, a plurality of package traces are embedded in the insulating layer and connected to the other end of the holes. The holes function as a positioning setting for connecting the solder balls to the package traces, such that the signal of the semiconductor chip is connected to the package trace via conductor of the chip, and further transmitted externally via solder ball. The elastic modulus of the material of the first insulating layer is preferably larger than 1.0 GPa.Type: ApplicationFiled: September 14, 2007Publication date: June 19, 2008Applicant: ADVANPACK SOLUTIONS PTE LTD.Inventors: Hwee-Seng Jimmy Chew, Chee Kian Ong, Bin Chichik Abd. Razak
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Publication number: 20080088013Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has an active surface. The semiconductor device includes at least a connecting element and at least a bump. The connecting element is disposed on the activate surface and has a minimum dimension smaller than 100 microns. The bump is disposed on the connecting element and is electrically connected to the active surface by the connecting element. The bump includes a pillar part disposed on the connecting element and a top part disposed at the top of the pillar part. The pillar part has a first dimension and a second dimension both parallel to the active surface. The first dimension is longer than 1.2 times the second dimension. The top part is composed of solder and will melt under the determined temperature. The pillar part will not melt under a determined temperature.Type: ApplicationFiled: October 1, 2007Publication date: April 17, 2008Applicant: ADVANPACK SOLUTONS PTE LTD.Inventors: Hwee-Seng Jimmy Chew, Chee Kian Ong