Semiconductor device carrier for fine pitch packaging miniaturization and manufacturing method thereof
A semiconductor package and a manufacturing method thereof are provided. The package element has a first insulating layer, and a plurality of holes are disposed on the first surface of the first insulating layer. Besides, a plurality of package traces are embedded in the insulating layer and connected to the other end of the holes. The holes function as a positioning setting for connecting the solder balls to the package traces, such that the signal of the semiconductor chip is connected to the package trace via conductor of the chip, and further transmitted externally via solder ball. The elastic modulus of the material of the first insulating layer is preferably larger than 1.0 GPa.
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This is a Continuation of U.S. application Ser. No. 11/898,717, filed Sep. 14, 2007, which was a Continuation-in-part of U.S. application Ser. No. 11/882,194, filed Jul. 31, 2007 the subject matters of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION1. Field of the Invention
The invention relates in general to a semiconductor package and manufacturing method thereof, and more particularly to a semiconductor package whose lead frame can be independently isolated and transported during the manufacturing process.
2. Description of the Related Art
Along with the advance in science and technology, the demand for various electronic products is booming. Meanwhile, as miniaturization is expected of electronic products by consumers, the semiconductor element, a crucial element used in an electronic product, is also directed towards the design of miniaturization, and the reduction in the pitch and width of the circuit of a semiconductor element has always been an important direction in the semiconductor industry. However, in addition to the reduction in the pitch and width of the circuit inside a semiconductor chip, the chip package carrying the signal and extended to the external also plays an important part in the miniaturization of a semiconductor element. If the circuit and pitch of a semiconductor package can not be effectively reduced, the miniaturization in the size of a semiconductor element using the same will be very limited.
For example, the thickness of a metallic trace of a conventional package normally ranges between 120˜250 micrometer, and a package trace is formed after the process of micro-filming, exposure and etching. However, the etching process restricts the pitch and width of a circuit, and the undercutting effect will affect the reliability of the package trace. Therefore, the conventional lead frame of the package trace is not suitable to the miniaturization in semiconductor element.
Thus, how to resolve the above problem of element miniaturization and simplify the manufacturing process of the package has become an important direction in the research and development of semiconductor package.
SUMMARY OF THE INVENTIONAccording to a first aspect of an embodiment of the present invention, a semiconductor package is provided. The semiconductor package comprises a first insulating layer and a plurality of package traces, wherein a plurality of holes are disposed on a first surface of the first insulating layer, and the package traces are embedded in the insulating layer and connected to another end of the holes.
According to an aspect of another embodiment of the present invention, a semiconductor package is provided. The semiconductor package comprises a first insulating layer, a plurality of positioning units and a plurality of package traces. The elastic modulus of the first insulating layer is larger than 1.0 GPa. The positioning units are disposed on the first insulating layer. The package traces are disposed under the positioning unit.
According to an aspect of another embodiment of the present invention, a manufacturing method of a semiconductor package is provided. The manufacturing method comprises the following steps. Firstly, a carrier is provided. Next, a plurality of traces are formed on the carrier. Then, a first insulating layer is formed on the traces. Afterwards, a plurality of positioning units are formed on a first surface of the first insulating layer next, wherein the positioning unit contacts the trace directly.
According to an aspect of another embodiment of the present invention, a method of manufacturing a semiconductor package is provided. The method of manufacturing the semiconductor package comprises the following steps. Firstly, a carrier is provided. Then, a plurality of electrically isolated package trace layout units are formed by a first conductive layer, wherein the package trace layout unit is formed by a plurality of electrically isolated package traces. Afterwards, a patterned second conductive layer is formed on the first conductive layer. Then a first insulating layer is formed by a molding material and embedded in the first conductive layer and the second conductive layer. After that, part of the carrier is selectively removed.
The invention will become apparent from the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings.
Referring to
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As a plurality of protrusions disposed on the mold 23 correspond to the trace layer 20, a plurality of holes 22 are formed on a surface of the first insulating layer 21. Referring to
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The solder 41 enables the electrically connection between the conductor 42 and the trace layer 20 even more tightly, and avoids the occurrence of bubbles which occurs when a solder ball is used as the conductor 42 but can not completely fill up the hole 22.
On the other hand, the independent semiconductor package and the package of the chip 31 can be flexible. Referring to
Besides, the semiconductor package is also used in a multi-chip package. Referring to
Referring to
Each package trace layout unit 80 preferably has a fan-in or fan-out pattern. The first conductive layer 20 and the second conductive layer 41 can have different pitches to achieve the function of fine pitch.
Second EmbodimentReferring to
Referring to
The photo-resist layer 25 is removed such that a patterned first conductive layer 20′ and a second conductive layer 27 are obtained as indicated in
By way of etching, the carrier 19 is removed to obtain a semiconductor package before package as indicated in
Besides, the second conductive layer 27 can be pretreated to resolve the resin residue problem arising in a QFN package when the tape is removed.
Referring to
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The photo-resist layer 25 is removed such that a patterned first conductive layer 20′ and a second conductive layer 27 are obtained as indicated in
By way of etching, part of the carrier 19′ is selectly removed to obtain a semiconductor package before package as indicated in
Referring to
Afterwards, referring to
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The conductive layer 20 or 20′ (the package trace) is formed during the manufacturing process without applying extra process such as micro-filming, exposure and etching on the conductive layer, so that the conductive layer is not restricted by the etching pitch and the reliability of the package trace will not be affected by undercutting. However, the package trace meets the requirement of miniaturization in the semiconductor element better.
The package trace layout unit has a fan-in or fan-out pattern to achieve the function of fine pitch.
Moreover, the hole 22 (the positioning unit) makes the positioning setting of connecting the solder ball to the package element more precisely, and avoids the overflowing of the solder when melted.
Besides, the mold 23, and hole 22 (the positioning unit) are formed by using the material of the first insulating layer 21 directly, such that the first insulating layer 21 and the positioning unit are formed by one filling of the molding material, largely simplifying the manufacturing process of the semiconductor package.
Moreover, according to
Furthermore, the first insulating layer 21 uses a molding material as a carrier for the package trace pattern, therefore the package trace patterns are not connected by metallic traces and are different form conventional lead frame which has traces for connecting the package trace patterns. The insulating layer between the traces of the lead frame is simply used for insulating purpose and can not be used as a carrier. As a result, in the embodiments of the invention does not have the connecting traces for connecting the lead frame patterns, and each package has an individual pattern, and is easier for cutting.
In a conventional chip, the package traces are connected via metallic traces, therefore the package traces must be divided first before the chip can be tested individually. In the above embodiments, as each package trace pattern is electrically isolated and does not have metallic traces for connection, the chip still can be tested even after the chip is connected to the package trace, largely saving time and cost for testing.
While the invention has been described by way of example and in terms of a preferred embodiment, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures. For example, the first insulating layer 21, is not necessarily limited to one layer. Any one who is skilled in the technology of the invention can use several materials to compose a compound insulating layer in several times of formation or use the same material to compose an insulating layer in several times of formation, and such modifications are still within the scope of protection of the invention which is defined in the appended claims.
Claims
1. A semiconductor package, comprising:
- an insulating layer having a first surface and a second surface opposite the first surface, wherein a package trace layout comprising a plurality of traces is embedded in the insulating layer between the first surface and the second surface of the insulating layer, the plurality of traces are entirely exposed and recessed on the first surface of the insulating layer to form a recessed pattern such that an exposed surface of the embedded traces is not on the same plane as the first surface of the insulating layer;
- a semiconductor chip disposed on the first surface of the insulating layer and comprises a plurality of conductors connecting the semiconductor chip to the package trace layout, wherein an inner part of the package trace layout lies inside an area of the semiconductor chip, the conductors are disposed between the semiconductor chip and the inner part of the package trace layout, and extend from a surface of the semiconductor chip to the embedded traces of the inner part of the package trace layout; and
- an encapsulating layer disposed on the first surface of the insulating layer and encapsulates the semiconductor chip, wherein an outer part of the package trace layout lies outside the area of the semiconductor chip, the encapsulating layer further fills the trace pattern and encapsulates the embedded traces of the outer part of the package trace layout.
2. The semiconductor package according to claim 1, wherein the conductors connect to the embedded traces.
3. The semiconductor package according to claim 2, wherein each of the plurality of conductors is a pillar bump or a solder bump.
4. The semiconductor package according to claim 3, wherein each of the pillar bumps comprises a pillar part and a solder part, the solder part is connected to the exposed surface of the embedded traces in the recessed pattern, and the pillar part is above the recessed pattern and connects the solder part to the semiconductor chip.
5. The semiconductor package according to claim 1, wherein the embedded traces in the inner part of the package trace layout fan out to the outer part of the package trace layout.
6. A semiconductor package, comprising:
- an insulating layer having a first surface and a second surface opposite the first surface, wherein a package trace layout comprising a plurality of traces is embedded in the insulating layer between the first surface and the second surface of the insulating layer, the plurality of traces are entirely exposed and recessed on the first surface of the insulating layer to form a recessed pattern such that an exposed surface of the embedded traces is not on the same plane as the first surface of the insulating layer;
- a semiconductor chip disposed on the first surface of the insulating layer and comprises a plurality of wires connecting the semiconductor chip to the package trace layout, wherein an outer part of the package trace layout lies outside an area of the semiconductor chip, the wires extend from a surface of the semiconductor chip to the embedded traces of the outer part of the package trace layout; and
- an encapsulating layer disposed on the first surface of the insulating layer and encapsulates the semiconductor chip, wherein the encapsulating layer further fills the recessed pattern and encapsulates the embedded traces of the outer part of the package trace layout.
7. The semiconductor package according to claim 6, further comprising a plurality of conductive protrusions disposed on part of the exposed surface of the embedded traces in the recessed pattern and extend to or above the first surface of the insulating layer, wherein the wires are bonded to the conductive protrusions.
8. The semiconductor package according to claim 7, wherein the conductive protrusions comprise gold.
9. The semiconductor package according to claim 6, wherein the embedded traces in the outer part of the package trace layout fan in to the inner part of the package trace layout.
10. The semiconductor package according to claim 1 or 6, further comprising a plurality of pillars embedded in the insulating layer between the first surface and the second surface of the insulating layer, wherein the pillars are connected to the traces.
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Type: Grant
Filed: Nov 26, 2008
Date of Patent: Jul 19, 2016
Patent Publication Number: 20090102043
Assignee: ADVANPACK SOLUTIONS PTE LTD. (Singapore)
Inventors: Hwee-Seng Jimmy Chew (Singapore), Chee Kian Ong (Singapore), Bin Chichik Abd. Razak (Singapore)
Primary Examiner: Ermias Woldegeorgis
Application Number: 12/292,813
International Classification: H01L 23/48 (20060101); H01L 21/683 (20060101); H01L 23/498 (20060101); H01L 23/00 (20060101);