Abstract: A system, optical assembly, and optical communication system are disclosed. The optical assembly is disclosed as including an optoelectronic component having a predetermined shape and an optical module that permits light emitted by the optoelectronic component or travelling to the optoelectronic component to pass therethough. The optical module is further disclosed as including a first surface and an opposing second surface, the first surface of the optical module including a first mating feature to receive the optoelectronic component, and the second surface of the optical module including a receptacle to receive and align an optical fiber with the optoelectronic component.

Abstract: A system, optical assembly, and optical communication system are disclosed. The optical assembly is disclosed as including an optoelectronic component having a predetermined shape and an optical module that permits light emitted by the optoelectronic component or travelling to the optoelectronic component to pass therethough. The optical module is further disclosed as including a first surface and an opposing second surface, the first surface of the optical module including a first mating feature to receive the optoelectronic component, and the second surface of the optical module including a receptacle to receive and align an optical fiber with the optoelectronic component.

Abstract: Various VCSEL device packages and VCSEL array configurations are disclosed. In one example, a device contains two or more VCSELs, each VCSEL having a substantially triangular body. Such device packages allow for denser VCSEL array configurations than those provided by traditional VCSEL device packages. The denser VCSEL array configurations not only allow for more VCSELs to be batch manufactured per wafer but also allow for denser layouts on various mounting surfaces.

Abstract: Methods are provided for using masking techniques and plasma etching techniques to dice a compound semiconductor wafer into dies. Using these methods allows compound semiconductor die to be obtained that have smooth side walls, a variety of shapes and dimensions, and a variety of side wall profiles. In addition, by using these techniques to perform the dicing operations, the locations of features of the die relative to the side walls are ascertainable with certainty such that one or more of the side walls can be used as a passive alignment feature to precisely align one or more of the die with an external device.

Abstract: Methods are provided for using masking techniques and plasma etching techniques to dice a compound semiconductor wafer into dies. Using these methods allows compound semiconductor die to be obtained that have smooth side walls, a variety of shapes and dimensions, and a variety of side wall profiles. In addition, by using these techniques to perform the dicing operations, the locations of features of the die relative to the side walls are ascertainable with certainty such that one or more of the side walls can be used as a passive alignment feature to precisely align one or more of the die with an external device.

Abstract: Methods are provided for using masking techniques and plasma etching techniques to dice a compound semiconductor wafer into dies. Using these methods allows compound semiconductor die to be obtained that have smooth side walls, a variety of shapes and dimensions, and a variety of side wall profiles. In addition, by using these techniques to perform the dicing operations, the locations of features of the die relative to the side walls are ascertainable with certainty such that one or more of the side walls can be used as a passive alignment feature to precisely align one or more of the die with an external device.