METHODS FOR DICING A COMPOUND SEMICONDUCTOR WAFER, AND DICED WAFERS AND DIE OBTAINED THEREBY
Methods are provided for using masking techniques and plasma etching techniques to dice a compound semiconductor wafer into dies. Using these methods allows compound semiconductor die to be obtained that have smooth side walls, a variety of shapes and dimensions, and a variety of side wall profiles. In addition, by using these techniques to perform the dicing operations, the locations of features of the die relative to the side walls are ascertainable with certainty such that one or more of the side walls can be used as a passive alignment feature to precisely align one or more of the die with an external device.
This application is a continuation application of application Ser. No. 13/758,265, filed on Feb. 4, 2013, originally entitled “METHODS FOR DICING A COMPOUND SEMICONDUCTOR WAFER, AND DICED WAFERS AND DIE OBTAINED THEREBY,” which has been allowed and which is hereby incorporated by reference herein in its entirety.
TECHNICAL FIELD OF THE INVENTIONThe invention relates to semiconductor wafers and processes. More particularly, the invention relates to methods for dicing a compound semiconductor wafer, and the diced wafers and die obtained by those methods.
BACKGROUND OF THE INVENTIONSemiconductor fabrication processes are multi-step processes that are used to create integrated circuits (ICs) that are used in a variety of applications. The process begins with the epitaxial growth of the wafer followed by many processing steps, such as deposition processes (e.g., chemical vapor deposition, molecular beam epitaxy, physical vapor deposition, atomic layer deposition), removal processes (e.g., wet etching, plasma etching, chemical-mechanical planarization), patterning processes (photolithography), and electrical property modification processes (e.g., diffusion, ion implantation). Typically, hundreds of such processing steps are performed to fabricate a wafer.
After the wafers have been fabricated, they are typically subjected to a variety of tests to verify that the wafers and the ICs formed on them meet certain standards. After testing, the wafers are diced to divide each wafer into many individual dies. Each die corresponds to an IC chip that will later be packaged in an IC package that is ready for use. Different dicing techniques are used, such as scoring and breaking, sawing, laser cutting, and etching.
With respect to scribing and breaking or sawing, it is difficult to achieve side walls for the dies that are very smooth. Rather, the side walls of the dies are often rough or jagged, which can eventually lead to mechanical defects being formed in the dies (e.g., through chipping or cracking). For example, typical sawing or cutting techniques can result in variations greater than 10 micrometers (microns) from die to die. In recent years, plasma etching tools and techniques have been used to perform the dicing operations on wafers. Using plasma etching for this purpose enables very precise dimensions for the dies to be obtained and can result in the dies having very smooth side walls.
SUMMARY OF THE INVENTIONThe invention provides a method for using a plasma etching process to dice compound semiconductor wafers into dies, compound semiconductor dies obtained thereby, and an array of passively-aligned compound semiconductor dies. The method comprises:
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- providing at least a first compound semiconductor die that has been diced from a compound semiconductor wafer by a plasma etch dicing process that provides the first die with at least one side wall that has a known spatial relationship to at least one element formed on or in a surface of the first CS die; and
- passively aligning the first CS die with an external device by placing the side wall in abutment with the external device. The known spatial relationship of the side wall to the element allows the side wall to be used as a passive alignment feature such that passively aligning the side wall with the external device results in passive alignment of the element of the die with the external device.
The compound semiconductor die of the invention is a die that has been diced by a plasma etch dicing process in such a way that a known spatial relationship is created between at least one side wall of the die and at least one element formed on or in a surface of the die. The known spatial relationship of said at least one side wall to said at least one element allows said at least one side wall to be used as a passive alignment feature such that passively aligning said at least one side wall with an external device results in passive alignment of said at least one element with the external device.
The array of compound semiconductor dies comprises compound semiconductor dies that have been diced from one or more compound semiconductor wafers by a plasma etch dicing process that provides each die with at least one side wall that has a known spatial relationship to at least one element formed on or in a surface of the respective die. The known spatial relationships allow the respective side walls to be used as respective passive alignment features such that passively aligning the respective side walls of the respective dies with one another results in passive alignment of the respective elements of the respective dies with one another.
These and other features and advantages of the invention will become apparent from the following description, drawings and claims.
In accordance with the invention, methods are provided that use masking techniques and plasma etching techniques to dice a compound semiconductor wafer. Using these systems and methods allow compound semiconductor die to be obtained that have smooth side walls, a variety of shapes and dimensions, and a variety of side wall profiles. In addition, by using these techniques to perform the dicing operations, the locations of features of the die relative to the side walls are ascertainable with certainty such that one or more of the side walls can be used as a passive alignment mechanism to precisely align features of the die with an external device. Illustrative embodiments of the methods, systems and the resulting dies will now be described with reference to the figures, in which like reference numerals represent like elements, components or features.
The first and second RF power sources 4 and 5 provide time-varying electrical currents that create time-varying magnetic fields about a rarefied gas (not shown) disposed in the chamber 2. The time-varying magnetic fields induce electrical currents in the gas to create a plasma 10. This process of creating plasma is referred to in the art as an inductively coupled plasma (ICP) process. The gas chemistry that is used in the chamber 2 is typically based on either a methane base (CH4) or a chlorine base (Cl2, BCl3). Different gas ratios are used to etch different types of compounds, and therefore the gas ratio that is used to etch the wafer 6 will depend on the compound comprising the wafer 6. The wafer compound is typically a III-V compound (i.e., made up of combination of two or more of Ga, As, Al, In, and Ph).
The wafer 30 having the patterned photoresist layer 40a-40c on it is then placed on an adhesive-bearing side of a piece of tape 50, as indicated by block 22 in
After the plasma etching process has been completed, the tape 50 having the wafer 30 thereon is removed from the chamber 2 and the remaining photoresist layer 40a-40c is removed using ashing and chemical rinse processes (not shown for purposes of clarity), leaving only the tape having the dies 30a, 30b and 30c thereon. This step is represented by block 24 in
Using the plasma etching process described above to dice the wafer 30 allows the dies to have any shape that can be defined by patterning photoresist, unlike conventional techniques used for dicing compound semiconductor wafers, which only allow dies having fixed rectangular shapes to be formed. In addition, using the plasma etching process results in the dies having very smooth side walls, which, as stated above, is generally not the case with conventional sawing or cutting singulation processes used for dicing compound semiconductor wafers. With the plasma etch dicing process, smoothness of the side walls is such that side wall variations from die to die are typically less than 10 microns, and often less than 5 microns. Furthermore, using the plasma etching process allows the dies to have any desired side wall profile.
In accordance with the invention, it has been determined that a plasma etching process such as described above with reference to
With the plasma etch dicing process, a variety of nonrectangular die shapes are obtainable, such as those shown in
In addition, the plasma etching need not be directional (i.e., straight down in a direction normal to the tape 200) in all cases. The gas chemistry may be changed during the etching process. Because different semiconductor compounds etch at different rates for different gas chemistries, using more than one gas chemistry during the etching process can result in different die shapes, such as the arched upper surfaces of the dies 230 and 240 and the curved side walls of die 210.
As indicated above, using plasma etching to dice the dies results in the dies having very smooth side walls compared to the relatively rough or jagged side walls of the dies that often result from dicing processes that use cutting or sawing. In accordance with embodiments of the invention, it has been determined that this characteristic of plasma-etched dies can be used to make a physical feature of the die, such as a side wall, for example, a passive alignment feature.
One way to avoid the risk of having to discard a die that contains multiple laser diodes due to one of the laser diodes being defective is to singulate the wafer into individual dies and then mount dies that are known to be non-defective in a side-by-side arrangement to form arrays of a desired size. Because the side walls of the dies can be made very smooth by using the plasma etch dicing process described above, the dies can be used as singlets 400 (
It should be noted that the invention has been described with respect to illustrative embodiments for the purpose of describing the principles and concepts of the invention. The invention is not limited to these embodiments. For example, while the invention has been described with reference to obtaining certain die shapes, the invention is not limited to the die shapes described herein or shown in the figures. Persons of skill in the art will understand, in view of the description being provided herein, that the processes described above can be varied to achieve a variety of other die shapes. Those skilled in the art will understand, in view of the description being provided herein, that many modifications may be made to the embodiments described herein while still achieving the goals of the invention and that all such modifications are within the scope of the invention.
Claims
1. A compound semiconductor die diced from a compound semiconductor wafer by a plasma etch dicing process in such a way that a known spatial relationship is created between at least one side wall of the die and at least one optical element formed on or in a surface of the die, and wherein the known spatial relationship between said at least one side wall and said at least one element allows said at least one side wall to be used as a passive alignment feature such that aligning said at least one side wall with a first alignment feature extending upwardly from a top surface of an external device results in alignment of said at least one optical element with the external device.
2. The compound semiconductor die of claim 1, wherein the die has a shape of a rectangle.
3. The compound semiconductor die of claim 1, wherein:
- the plasma etch dicing process that is used to dice the wafer provides the die with at least first and second side walls that have known spatial relationships to said at least one optical element and to one another, and
- the known spatial relationships allow the first and second side walls to be used as passive alignment features such that aligning the first side wall with the first alignment feature of the external device and aligning the second side wall with a second alignment feature extending upwardly from the top surface of the external device results in alignment of the external device with said at least one optical element.
4. The compound semiconductor die of claim 3, wherein the external device is an alignment base, and wherein the first and second alignment features each further include a first sidewall and second sidewall forming a right angle and the first alignment feature and second alignment feature are positioned on the top surface of the alignment base so as to receive the first die.
5. The compound semiconductor die of claim 4, wherein the alignment base is configured to be aligned with a second external structure such that the alignment of said at least one optical element with the alignment base results in alignment of said at least one optical element with the second external structure.
6. The compound semiconductor die of claim 3, wherein the first and second side walls are substantially perpendicular to one another, and wherein said at least one optical element is formed on or in a surface of the die that is substantially perpendicular to the first and second side walls.
7. The compound semiconductor die of claim 3, wherein the die has a shape of a rectangle, and wherein the first and second side walls are substantially parallel to one another and substantially perpendicular to said surface.
8. The compound semiconductor die of claim 1, wherein the die has a non-rectangular shape.
9. The compound semiconductor die of claim 1, wherein the die is a laser diode die and wherein said at least one optical element is a light-emitting facet of the die.
10. The compound semiconductor die of claim 1, wherein the die is a photodiode die and wherein said at least one optical element is a light-receiving facet of the die.
11. The compound semiconductor die of claim 1, wherein the external device is an alignment base and the first alignment feature further includes a first sidewall and a second sidewall forming a right angle configured to receive the die.
12. An array of compound semiconductor (CS) dies, wherein the CS dies have been diced from one or more CS wafers by a plasma etch dicing process that provides each CS die with at least one side wall that has a known spatial relationship to at least one optical element formed on or in a surface of the respective CS die, and wherein the known spatial relationships allow the respective side walls to be used as respective alignment features such that aligning the respective side walls of the respective CS dies with one another results in alignment of the respective optical elements of the respective CS dies with one another.
13. The array of claim 12, wherein at least two of the CS dies of the array have different dimensions.
14. The array of claim 12, wherein at least two of the CS dies of the array have different shapes.
15. The array of claim 12, wherein at least two of the CS dies have different functions.
16. The array of claim 12, wherein at least two of the CS dies are laser diode dies having different operating wavelengths.
17. The array of claim 12, wherein at least two of the CS dies are photodiode dies having different operating wavelengths.
18. The array of claim 12, wherein at least one of the CS dies is laser diode die and at least one of the CS dies is a photodiode, and wherein said optical element of the laser diode is a light-emitting facet and wherein said optical element of the photodiode is a light-receiving facet.
19. The array of claim 12, wherein at least two of the CS dies have been diced from different CS wafers and are made of different materials.
20. The array of claim 12, wherein at least two of the CS dies have been diced from a same CS wafer and are made of a same material.
Type: Application
Filed: Dec 16, 2014
Publication Date: Apr 9, 2015
Inventors: Chee Siong Peh (Singapore), Chiew Hai NG (Singapore), David G. McIntyre (Singapore)
Application Number: 14/572,371
International Classification: H01L 25/16 (20060101); H01S 5/40 (20060101); H01S 5/02 (20060101); H01L 25/04 (20060101); H01L 31/0232 (20060101);