Patents by Inventor Chee Wai
Chee Wai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160164668Abstract: Techniques to operate circuitry in an integrated circuit are provided. The circuitry may include a receiver circuit and one of the provided techniques includes receiving a data stream at the receiver circuit. The receiver circuit may include a detector circuit that is used to determine the data rate of the received data stream. A controller block in the receiver circuit may accordingly configure a deserializer circuit in the receiver circuit based on the data rate of the received data stream. The circuitry may further include a transmitter circuit for transmitting data streams. The transmitter circuit may be configured during runtime based on the data rate of a data stream that is being transmitted. In some instances, irrespective of the data rate of the data stream being transmitted, a constant reference clock may be used in the transmitter circuit.Type: ApplicationFiled: February 18, 2016Publication date: June 9, 2016Inventors: Boon Hong Oh, Chee Wai Yap
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Patent number: 9300463Abstract: Techniques to operate circuitry in an integrated circuit are provided. The circuitry may include a receiver circuit and one of the provided techniques includes receiving a data stream at the receiver circuit. The receiver circuit may include a detector circuit that is used to determine the data rate of the received data stream. A controller block in the receiver circuit may accordingly configure a deserializer circuit in the receiver circuit based on the data rate of the received data stream. The circuitry may further include a transmitter circuit for transmitting data streams. The transmitter circuit may be configured during runtime based on the data rate of a data stream that is being transmitted. In some instances, irrespective of the data rate of the data stream being transmitted, a constant reference clock may be used in the transmitter circuit.Type: GrantFiled: May 6, 2014Date of Patent: March 29, 2016Assignee: Altera CorporationInventors: Boon Hong Oh, Chee Wai Yap
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Patent number: 9197210Abstract: Apparatuses for reducing power consumption in a programmable logic device (PLD) with a self power down mechanism are disclosed. Methods and a machine readable medium for restoring a prior known state are provided. The prior known state is stored in a memory module before the PLD is powered down and the same state is restored from the memory module when the PLD is powered up. The memory module may be an internal or an external non-volatile or volatile memory source. One sector of the memory may be used to store the previous known state. The memory sector can be partitioned into different sections. One section may be used as a header section associated with a data storage section. Partitioning the memory sector into different sections and utilizing multiple addresses from each section ensure less read and write cycles during the powering down and the powering up of the PLD.Type: GrantFiled: March 24, 2014Date of Patent: November 24, 2015Assignee: Altera CorporationInventor: Chee Wai Yap
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Publication number: 20150329829Abstract: The invention discloses a methodology for the culture of prostate tissue organoids from mouse and human prostate.Type: ApplicationFiled: May 26, 2015Publication date: November 19, 2015Inventors: Michael M. SHEN, Chee Wai CHUA, Ming LEI
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Patent number: 9166590Abstract: An integrated circuit may include memory interface circuitry that interfaces with memory. The integrated circuit may include calibration circuitry and storage circuitry. The calibration circuitry may have a first configuration in which the calibration circuitry is formed from a first set of programmable logic regions that configure the calibration circuitry to generate and store calibration data at the storage circuitry. The calibration data may include strobe signal phase settings and read enable control signal timing settings. The calibration circuitry may have a second configuration in which the calibration circuitry is formed from a second set of programmable logic regions that configure the calibration circuitry to load the calibration data from the storage circuitry and to interface with the memory based on the calibration data. The calibration circuitry may occupy fewer programmable logic regions on the integrated circuit in the second configuration than in the first configuration.Type: GrantFiled: January 23, 2014Date of Patent: October 20, 2015Assignee: Altera CorporationInventors: Chee Wai Yap, Muhamad Aidil Jazmi
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Publication number: 20150288511Abstract: Techniques to operate circuitry in an integrated circuit are provided. The circuitry may include a receiver circuit and one of the provided techniques includes receiving a data stream at the receiver circuit. The receiver circuit may include a detector circuit that is used to determine the data rate of the received data stream. A controller block in the receiver circuit may accordingly configure a deserializer circuit in the receiver circuit based on the data rate of the received data stream. The circuitry may further include a transmitter circuit for transmitting data streams. The transmitter circuit may be configured during runtime based on the data rate of a data stream that is being transmitted. In some instances, irrespective of the data rate of the data stream being transmitted, a constant reference clock may be used in the transmitter circuit.Type: ApplicationFiled: May 6, 2014Publication date: October 8, 2015Applicant: Altera CorporationInventors: Boon Hong Oh, Chee Wai Yap
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Patent number: 8717062Abstract: Apparatuses for reducing power consumption in a programmable logic device (PLD) with a self power down mechanism are disclosed. Methods and a machine readable medium for restoring a prior known state are provided. The prior known state is stored in a memory module before the PLD is powered down and the same state is restored from the memory module when the PLD is powered up. The memory module may be an internal or an external non-volatile or volatile memory source. One sector of the memory may be used to store the previous known state. The memory sector can be partitioned into different sections. One section may be used as a header section associated with a data storage section. Partitioning the memory sector into different sections and utilizing multiple addresses from each section ensure less read and write cycles during the powering down and the powering up of the PLD.Type: GrantFiled: January 18, 2012Date of Patent: May 6, 2014Assignee: Altera CorporationInventor: Chee Wai Yap
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Publication number: 20140111406Abstract: An electroluminescent display panel includes a plurality of sub-pixels; a plurality of scan lines, each of the scan lines being electrically connected to a first row of sub-pixels and a second row of sub-pixels of two adjacent rows; a plurality of first data lines electrically connected to the first rows of sub-pixels of corresponding columns respectively; a plurality of second data lines electrically connected to the second rows of sub-pixels of corresponding columns respectively; a scan driving unit for outputting a plurality of scanning signals; and a data driving unit for outputting a plurality of dada signals; wherein the scanning signals sequentially turn on two adjacent rows of sub-pixels via the scan lines, the data signals on the first data lines charge the first rows of sub-pixels of the corresponding columns, and the data signals on the second data lines charge the second rows of sub-pixels of the corresponding columns.Type: ApplicationFiled: July 5, 2013Publication date: April 24, 2014Inventors: Tsang-Hong Wang, Chee-Wai Lau
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Patent number: 8698492Abstract: Methods for testing for defects on magnetic media storage disks are provided. One such method includes dividing a surface of a magnetic media disk into a plurality of radial zones, dividing the disk surface into a plurality of concentric zones, thereby forming a preselected number (N) of wedge subsections for each of the concentric zones, scanning the disk surface for defects, counting the defects contained within each of the wedge subsections, summing the defects contained within two or more of the wedge subsections, comparing the summed defects with a preselected threshold, and determining, based on the comparison, a defect type of the disk.Type: GrantFiled: January 11, 2012Date of Patent: April 15, 2014Assignee: Western Digital Technologies, Inc.Inventors: Chee Wai Mak, Surasith Phongtharapat, Chalermchai Suchatpong
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Patent number: 8621041Abstract: Embodiments of the present invention address deficiencies of the art in respect to Web services construction and provide a novel and non-obvious method, system and computer program product for message-oriented Web services construction. A method for the message oriented construction of a Web service can include graphically assembling a selection of message flow primitives defining an operation for a Web service, interconnecting selected ones of the message flow primitives to represent a flow of messages from one interconnected message flow primitive to another interconnected message flow primitive, and generating Web service logic from the selection of message flow primitives. The method further can include interpreting or executing the Web service logic in response to receiving a request to invoke the Web service.Type: GrantFiled: November 15, 2006Date of Patent: December 31, 2013Assignee: International Business Machines CorporationInventors: Allen Vi Chan, Zhongming Chen, Phil Coulthard, Richard Myer Goldberg, Elaine Yin Ling Lau, Chee Wai Ooi, David Adiel Spriet
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Patent number: 8575579Abstract: A proton beam collimator comprising (a) titanium or (b) stainless steel containing no tungsten or (c) containing no tungsten or brass. The collimator comprises a multi-leaf collimator (MLC). The apparatus further comprises an integrated circuit (IC) mounted adjacent the collimator, the IC subject to exposure to atomic particles, illustratively, neutrons.Type: GrantFiled: March 26, 2012Date of Patent: November 5, 2013Assignee: Indiana University Research and Technololgy CorporationInventors: Vadim Moskvin, Chee Wai Cheng
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Patent number: 8483027Abstract: A disk drive is disclosed comprising a disk including a plurality of tracks, a head coupled to an actuator arm actuated over the disk, and control circuitry operable to first seek the head from a first track to a second track, read data from the second track to generate a first read signal, second seek the head from the second track to a third track, read data from the third track to generate a second read signal, third seek the head from the third track to a fourth track, and read data from the fourth track to generate a third read signal. The first, second, and third read signals are evaluated to qualify the disk drive, wherein the first, second, and third seeks are executed in proximity so as to excite the actuator arm with a jitter motion.Type: GrantFiled: May 25, 2011Date of Patent: July 9, 2013Assignee: Western Digital Technologies, Inc.Inventors: Chee Wai Mak, Chee Wai Lau, Suttisak Nilchim, Burin Jindasuay, Pramook Toworachot
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Publication number: 20130168706Abstract: An array of light emitting devices and a method for large area fabrication of such is provided. The method includes providing a continuous flexible substrate and printing one or more layers of light emitting devices comprised of layers of transparent conductor, light emitting material, dielectric and electrode on the flexible substrate. The array of light emitting devices includes a flexible substrate and one or more layers of light emitting devices on the flexible substrate. The one or more layers of light emitting devices include layers of transparent conductor, light emitting material, dielectric and electrode.Type: ApplicationFiled: September 7, 2012Publication date: July 4, 2013Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCHInventors: Budiman Salam, Chee Wai Albert Lu, Boon Keng Lok, Lia Lal Wai
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Publication number: 20130141877Abstract: A fan-out circuit electrically connected to a driver and a plurality of signal lines is provided. The fan-out circuit includes a first fan-out trace including a first and a second conductive line, and a second fan-out trace including a third and a fourth conductive line. The second conductive line is connected between the first conductive line and one of the signal lines. The length of the second and fourth conductive lines are L1? and L2? respectively. An obtuse included angle is formed between the first and second conductive lines. The width of the first and third conductive lines is W1. The fourth conductive line is electrically connected to the third conductive line and another one of the signal lines. The obtuse included angle is formed between the third and fourth conductive lines. The width of the second and fourth conductive lines is W2, and (W2/L1?)>(W2/L2?) and L1?<L2?.Type: ApplicationFiled: April 12, 2012Publication date: June 6, 2013Applicant: AU OPTRONICS CORPORATIONInventors: Chee-Wai Lau, Tsao-Wen Lu, Chien-Ju Lin, Chien-Hao Fu, Tsang-Hong Wang
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Publication number: 20130072744Abstract: A proton beam collimator comprising (a) titanium or (b) stainless steel containing no tungsten or (c) containing no tungsten or brass. The collimator comprises a multi-leaf collimator (MLC). The apparatus further comprises an integrated circuit (IC) mounted adjacent the collimator, the IC subject to exposure to atomic particles, illustratively, neutrons.Type: ApplicationFiled: March 26, 2012Publication date: March 21, 2013Inventors: Vadim Moskvin, Chee Wai Cheng
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Publication number: 20120146981Abstract: A driving method for a display apparatus. The display apparatus includes a plurality of first pixel units, a plurality of second pixel units, a first group of transmission lines and a second group of transmission lines. The first group of transmission lines and the second group of transmission lines are electronically connected to the plurality of first pixel units and the plurality of second pixel units, respectively. The driving method includes: generating a first and a second input signals including a plurality of input signals each having an identical waveform; and transmitting the first and the second input signals into the first group and second group of transmission lines such that the first and second input signals are transmitted to the plurality of first pixel units and the plurality of second pixel units in a plurality of different transmission directions, respectively.Type: ApplicationFiled: November 23, 2011Publication date: June 14, 2012Inventors: Chee-Wai Lau, Cheng-Nan Yeh, Tsang-Hong Wang
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Publication number: 20120112789Abstract: Apparatuses for reducing power consumption in a programmable logic device (PLD) with a self power down mechanism are disclosed. Methods and a machine readable medium for restoring a prior known state are provided. The prior known state is stored in a memory module before the PLD is powered down and the same state is restored from the memory module when the PLD is powered up. The memory module may be an internal or an external non-volatile or volatile memory source. One sector of the memory may be used to store the previous known state. The memory sector can be partitioned into different sections. One section may be used as a header section associated with a data storage section. Partitioning the memory sector into different sections and utilizing multiple addresses from each section ensure less read and write cycles during the powering down and the powering up of the PLD.Type: ApplicationFiled: January 18, 2012Publication date: May 10, 2012Inventor: Chee Wai Yap
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Patent number: 8159413Abstract: In a double-stacked electromagnetic bandgap (EBG) structure, a first conductive plane and a second conductive plane are spaced apart in parallel. At least two EBG layers are embedded in parallel between the first conductive plane and the second conductive plane. The at least two EBG layers have different stopband characteristics. A plurality of vias connect the at least two EBG layers respectively to one of the first and second conductive planes. At least the vias connecting one of the EBG layers pass through via holes in cells of another EBG layer.Type: GrantFiled: November 1, 2006Date of Patent: April 17, 2012Assignee: Agency for Science, Technology and ResearchInventors: Jongbae Park, Chee Wai Albert Lu, Joungho Kim
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Publication number: 20120063973Abstract: In an embodiment, a flexible fluid storage and warming bag may be provided. The flexible fluid storage and warming bag may include two flexible main walls, each including a surrounding edge, the two flexible main walls overlapping each other and being fluid-tightly sealed together along the surrounding edges thereof, the bag including a single non-partitioned fluid chamber defined by and between the two flexible main walls and by the sealed surrounding edges; at least one fluid transfer port extending into the single non-partitioned fluid chamber and being configured to allow transfer of the fluid into and out of the bag; and an electrical heating element integrated with at least one of the two flexible main walls of the bag. A fluid storage and warming system may also be provided.Type: ApplicationFiled: May 21, 2010Publication date: March 15, 2012Applicant: Agency for Science, Technology and ResearchInventors: Gim Ching Jenny Ang, Joo Chuan Yeo, Chee Wai Albert Lu, Chee Wai Patrick Shi
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Patent number: 8106680Abstract: Apparatuses for reducing power consumption in a programmable logic device (PLD) with a self power down mechanism are disclosed. Methods and a machine readable medium for restoring a prior known state are provided. The prior known state is stored in a memory module before the PLD is powered down and the same state is restored from the memory module when the PLD is powered up. The memory module may be an internal or an external non-volatile or volatile memory source. One sector of the memory may be used to store the previous known state. The memory sector can be partitioned into different sections. One section may be used as a header section associated with a data storage section. Partitioning the memory sector into different sections and utilizing multiple addresses from each section ensure less read and write cycles during the powering down and the powering up of the PLD.Type: GrantFiled: July 11, 2008Date of Patent: January 31, 2012Assignee: Altera CorporationInventor: Chee Wai Yap