Abstract: The present invention discloses a method for fabricating multiple-thickness insulator layers via strain field generated by stress. The strain field is used for alternating a develop mechanism of insulator layers on the quantum dots. By forming the multiple-thickness insulator layers at various developing rates, not only leakage current is prevented, but also components are kept isolated in the nano-electronics components. In nano-electronics manufacturing, the method for fabricating multiple-thickness insulator layers results in both better product reliability and the yield rate. It is potential for integral circuit manufacturing.

Abstract: A structure of the relaxed SiGe epitaxial layer and a fabrication method comprises a Si substrate, a Si interfacial layer positioning on the substrate, a SiGe graded buffer layer positioning on the Si interfacial layer, and a uniform SiGe epitaxy layer positioning on the SiGe graded buffer layer. It uses a mesa structure and obtains a highly relaxed SiGe epitaxial layer with a low defect density of threading dislocations, a smooth surface. A strained Si can be formed on the strained relaxation layer. The strained Si, the strained Ge, the strained Si/Ge can apply to the high-speed planar electronic devices. By using a mesa structure, it can efficiently decrease the required growth time and cost in the conventional relaxed SiGe epitaxy layer.

Abstract: An avalanche photo-detector (APD) is disclosed, which can reduce device capacitance, operating voltage, carrier transport time and dark current as well as increasing response speed and output power. Thus, an avalanche photo-detector (APD) with high saturation power, high gain-bandwidth product, low noise, fast response, low dark current is achieved. The APD includes an absorption layer with graded doping for converting an incident light into carriers, an undoped multiplication layer for multiplying current by means of receiving carriers, a doped field buffer layer sandwiched between the absorption layer and the multiplication layer for concentrating an electric field in the multiplication layer when a bias voltage is applied, and an undoped drift layer sandwiched between the absorption layer and the field buffer layer for capacitance reduction.

Abstract: A method for growing strained Si layer and relaxed SiGe layer with multiple Ge quantum dots (QDs) on a substrate is disclosed. The method can reduce threading dislocation density, decrease surface roughness of the strained silicon and further shorten growth time for forming epitaxy layers than conventional method. The method includes steps of: providing a silicon substrate, forming a multiple Ge QDs layers; forming a layer of relaxed SixGe1-x; and forming a strained silicon layer in subsequence; wherein x is greater than 0 and less than 1.

Abstract: A MOSFET structure utilizing strained silicon carbon alloy and fabrication method thereof. The MOSFET structure includes a substrate, a graded SiGe layer, a relaxed buffer layer, a strained silicon carbon alloy channel layer, a gate dielectric layer, a polysilicon gate electrode (or metal gate electrode) and a source/drain region.

Abstract: A method for characterizing the quality of the interface between a silicon and a gate insulator in a MOS device includes the steps of: applying at least one current to the MOS device through the gate; detecting at least one electroluminescent signal corresponding to the silicon bandgap energy after the current flows through the MOS device; and outputting the electroluminescent waveform in the time domain. The quality of the interface between a silicon and a gate insulator in the MOS device is determined by analyzing the minority carrier lifetime in silicon. The invention also discloses a characterization system for implementing the method.

Abstract: An infrared photodetector formed of a MOS tunneling diode is disclosed. The infrared photodetector comprises a conducting layer, a semiconductor layer comprising at least one layer of quantum structure for confining a carrier in a barrier, an insulating layer formed between the conducting layer and the semiconductor layer, and a voltage source connected to the conducting layer and the semiconductor layer for providing a bias voltage to generate a quantum tunneling effect, such that the carrier penetrates through the insulating layer to form a current, wherein when irradiated by an infrared, the carrier in the barrier absorbs the energy of the infrared to jump out of the barrier and is collected by an electrode to form a photocurrent.

Abstract: Strained Si surrounding the SiGe embedded body on a SOI (silicon on insulator) substrate forms a novel FinFET. The mobility in the channel is enhanced due to strain of the Si channel. The strained Si FinFET includes a SOI substrate, an SiGe embedded body, a strained Si channel surrounding layer, an oxide layer, a poly Si gate electrode (or metal gate electrode), a source and a drain.

Abstract: A method for utilizing a rough insulator to enhance metal-insulator-semiconductor reliability is provided. The method includes steps of: (a) providing a semiconductor substrate; (b) prebaking the semiconductor substrate under a relatively high vacuum to form a rough surface on the semiconductor substrate; and (c) growing an insulator on the semiconductor substrate to form a rough insulator and increase the metal-insulator-semiconductor reliability when the insulator is applied.

Abstract: The present invention discloses a method for fabricating multiple-thickness insulator layers via strain field generated by stress. The strain field is used for alternating a develop mechanism of insulator layers on the quantum dots. By forming the multiple-thickness insulator layers at various developing rates, not only leakage current is prevented, but also components are kept isolated in the nano-electronics components. In nano-electronics manufacturing, the method for fabricating multiple-thickness insulator layers results in both better product reliability and the yield rate. It is potential for integral circuit manufacturing.

Abstract: A phototransistor structure is disclosed. A sidewall is grown on the collector side and under the base. The surface of the sidewall is formed with a sidewall contact. When the contact is connected to an external voltage, the holes accumulated at the junction of the base and emitter can be quickly removed. This solves the problem in the prior art that using a bias between the base and the emitter to remove holes usually results in a large dark current (bias current), power consumption, and diminishing optoelectronic conversion gain.

Abstract: A manufacture method of a semiconductor device, and more particularly to the manufacture method of a silicon/silicon-germanium heterogeneous bipolar transistor (HBT) device with ultra-thin base, which mainly utilized the method of doping carbon atoms in the silicon-germanium (SiGe) spacer layer in order to suppress the out-diffusion of boron, increase the amount of doped boron in base, germanium (Ge) concentration, and critical thickness, and decrease the thickness of silicon-germanium spacer layer, and achieve the objective of raising the device's high frequency property.

Abstract: A method of gas switching in a rapid thermal process for improving the reliability of an insulation layer is disclosed. The method includes steps of providing a silicon substrate; introducing a process gas; rapidly heating said silicon substrate to a process temperature for producing an insulation layer on said silicon substrate; and immediately stopping introducing said process gas in a moment of switching to reduce said process temperature for preventing said silicon substrate from producing an insulation layer.

Abstract: A method for utilizing a rough insulator to enhance metal-insulator-semiconductor reliability is provided. The method includes steps of: (a) providing a semiconductor substrate; (b) prebaking the semiconductor substrate under a relatively high vacuum to form a rough surface on the semiconductor substrate; and (c) growing an insulator on the semiconductor substrate to form a rough insulator and increase the metal-insulator-semiconductor reliability when the insulator is applied.

Abstract: A method for characterizing the quality of the interface between a silicon and a gate insulator in a MOS device includes the steps of: applying at least one current to the MOS device through the gate; detecting at least one electroluminescent signal corresponding to the silicon bandgap energy after the current flows through the MOS device; and outputting the electroluminescent waveform in the time domain. The quality of the interface between a silicon and a gate insulator in the MOS device is determined by analyzing the minority carrier lifetime in silicon. The invention also discloses a characterization system for implementing the method.

Abstract: A reflector structure is provided for improving irradiation uniformity of a linear lamp array applied in a semiconductor process. The reflector structure includes a central reflector, two side reflectors, and two inclined reflectors. The central reflector is horizontally set above the linear lamp array at a first predetermined distance from a wafer for reflecting light irradiated from a central part of the linear lamp array to the wafer. The two side reflectors are horizontally set above the linear lamp at a second predetermined distance to the wafer, wherein the second predetermined distance is less than the first predetermined distance, and respectively connected to two opposite side parts of the central reflector for reflecting light irradiated from side parts of the linear lamp array to the wafer.