Patents by Inventor Chee-Wee Liu

Chee-Wee Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Transistor with wurtzite channel
    Patent number: 9679961
    Abstract: A device includes a source region, a drain region, and a wurtzite semiconductor between the source region and the drain region. A source-drain direction is parallel to a [01-10] direction or a [?2110] direction of the wurtzite semiconductor. The device further includes a gate dielectric over the wurtzite semiconductor, and a gate electrode over the gate dielectric.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: June 13, 2017
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Taiwan University
    Inventors: Hung-Chih Chang, Pin-Shiang Chen, Chee-Wee Liu, Samuel C. Pan
  • 3D UTB transistor using 2D-material channels
    Patent number: 9660056
    Abstract: A semiconductor device and a method of manufacture are provided. A substrate has a dielectric layer formed thereon. A three-dimensional feature, such as a trench or a fin, is formed in the dielectric layer. A two-dimensional layer, such as a layer (or multilayer) of graphene, transition metal dichalcogenides (TMDs), or boron nitride (BN), is formed over sidewalls of the feature. The two-dimensional layer may also extend along horizontal surfaces, such as along a bottom of the trench or along horizontal surfaces of the dielectric layer extending away from the three-dimensional feature. A gate dielectric layer is formed over the two-dimensional layer and a gate electrode is formed over the gate dielectric layer. Source/drain contacts are electrically coupled to the two-dimensional layer on opposing sides of the gate electrode.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: May 23, 2017
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Taiwan University
    Inventors: Hung-Chih Chang, Pin-Shiang Chen, Chee-Wee Liu
  • Negative Capacitance Field Effect Transistor With Charged Dielectric Material
    Publication number: 20170141235
    Abstract: The present disclosure provides a semiconductor device in accordance with some embodiments. The semiconductor device includes a substrate; a gate stack over the substrate. The gate stack includes a ferroelectric layer; a first dielectric material layer; and a first conductive layer. One of the first dielectric material layer and the ferroelectric layer is electrically charged to form a charged layer with fixed charge. The semiconductor device further includes source and drain features formed on the substrate and disposed on sides of the gate stack.
    Type: Application
    Filed: November 16, 2015
    Publication date: May 18, 2017
    Inventors: Der-Chuan Lai, Samuel C. Pan, Yu-Cheng Shen, Min-Hung Lee, Chee-Wee Liu
  • Semiconductor devices and manufacturing methods thereof
    Patent number: 9646994
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a first fin field effect transistor (FinFET) disposed over a substrate, and a second FinFET device disposed over the first FinFET. A junction isolation material is disposed between a source of the first FinFET and a source of the second FinFET.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: May 9, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chee-Wee Liu, Hung-Chih Chang, Cheng-Yi Peng, Chih-Sheng Chang
  • Three-dimensional transistor and methods of manufacturing thereof
    Patent number: 9627411
    Abstract: Three-dimensional (3D) transistors and methods of manufacturing thereof include a first semiconductor fin extending over a substrate. The first semiconductor fin has a vertical recess extending from a first sidewall of the first semiconductor fin toward a second sidewall of the first semiconductor fin opposite the first sidewall. A distance between two opposing sidewalls of the vertical recess decreases as the vertical recess extends toward the second sidewall of the first semiconductor fin. The device further includes a vertically recessed channel region between the second sidewall of the first semiconductor fin and a bottom of the vertical recess, source/drain (S/D) regions at opposite ends of the vertically recessed channel region, and a gate stack over the vertically recessed channel region.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: April 18, 2017
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Taiwan University
    Inventors: Jhih-Yang Yan, Samuel C. Pan, Chee Wee Liu, Hung-Yu Yeh, Da-Zhi Zhang
  • Field Effect Transistors and Methods of Forming Same
    Publication number: 20170098706
    Abstract: Semiconductor devices and methods of forming the same are provided. A first source/drain layer is formed over a substrate. A channel layer is formed over the first source/drain layer. A second source/drain layer is formed over the channel layer. The first source/drain layer, the channel layer, and the second source/drain layer are patterned to form a fin-shaped structure. A gate stack is formed on a sidewall of the fin-shaped structure. The fin-shaped structure is patterned to expose a top surface of the first source/drain layer.
    Type: Application
    Filed: December 15, 2016
    Publication date: April 6, 2017
    Inventors: Chee Wee Liu, Samuel C. Pan, I-Hsieh Wong, Hung-Yu Yeh
  • Semiconductor structure with interfacial layer and method for manufacturing the same
    Patent number: 9595593
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and an interfacial layer formed over the substrate. The semiconductor structure further includes a gate structure formed over the interfacial layer. In addition, the interfacial layer is made of metal germanium oxide, metal silicon oxide, or metal germanium silicon oxide and is in direct contact with a top surface of the substrate.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: March 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Fan Lee, Chee-Wee Liu, Chin-Kun Wang, Yuh-Ta Fan, Chih-Hsiung Huang, Tzu-Yao Lin
  • FIELD EFFECT TRANSISTORS AND METHODS OF FORMING SAME
    Publication number: 20170040418
    Abstract: Semiconductor devices and methods of forming the same are provided. A first gate electrode layer is formed over a substrate. A first gate dielectric layer is formed over the first gate electrode layer. A first channel layer is formed over the first gate dielectric layer. An isolation layer is formed over the first channel layer. A second channel layer is formed over the isolation layer. A second gate dielectric layer is formed over the second channel layer. The second gate dielectric layer, the second channel layer, the isolation layer and the first channel layer are patterned to form a first opening, the first opening extending through the first gate dielectric layer, the second channel layer and the isolation layer, and into the first channel layer. A first source/drain region is formed in the first opening.
    Type: Application
    Filed: October 21, 2016
    Publication date: February 9, 2017
    Inventors: Pin-Shiang Chen, Samuel C. Pan, Chee-Wee Liu, Sheng-Ting Fan
  • Field effect transistors and methods of forming same
    Patent number: 9559168
    Abstract: Semiconductor devices and methods of forming the same are provided. A first gate stack is formed over a substrate, wherein the first gate stack comprises a first ferroelectric layer. A source/channel/drain stack is formed over the first gate stack, wherein the source/channel/drain stack comprises one or more 2D material layers. A second gate stack is formed over the source/channel/drain stack, wherein the second gate stack comprises a second ferroelectric layer.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: January 31, 2017
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Taiwan University
    Inventors: Der-Chuan Lai, Pin-Shiang Chen, Hung-Chih Chang, Chee-Wee Liu, Samuel C. Pan
  • Field effect transistors and methods of forming same
    Patent number: 9559209
    Abstract: Semiconductor devices and methods of forming the same are provided. A first source/drain layer is formed over a substrate. A channel layer is formed over the first source/drain layer. A second source/drain layer is formed over the channel layer. The first source/drain layer, the channel layer, and the second source/drain layer are patterned to form a fin-shaped structure. A gate stack is formed on a sidewall of the fin-shaped structure. The fin-shaped structure is patterned to expose a top surface of the first source/drain layer.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: January 31, 2017
    Assignees: Taiwan Semiconductor Manufacturing Company Ltd., National Taiwan University
    Inventors: Chee Wee Liu, Samuel C. Pan, I-Hsieh Wong, Hung-Yu Yeh
  • SEMICONDUCTOR STRUCTURE WITH INTERFACIAL LAYER AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20160380069
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and an interfacial layer formed over the substrate. The semiconductor structure further includes a gate structure formed over the interfacial layer. In addition, the interfacial layer is made of metal germanium oxide, metal silicon oxide, or metal germanium silicon oxide and is in direct contact with a top surface of the substrate.
    Type: Application
    Filed: June 29, 2015
    Publication date: December 29, 2016
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Wei-Fan LEE, Chee-Wee LIU, Chin-Kun WANG, Yuh-Ta FAN, Chih-Hsiung HUANG, Tzu-Yao LIN
  • FIELD EFFECT TRANSISTORS AND METHODS OF FORMING SAME
    Publication number: 20160365457
    Abstract: Semiconductor devices and methods of forming the same are provided. A first source/drain layer is formed over a substrate. A channel layer is formed over the first source/drain layer. A second source/drain layer is formed over the channel layer. The first source/drain layer, the channel layer, and the second source/drain layer are patterned to form a fin-shaped structure. A gate stack is formed on a sidewall of the fin-shaped structure. The fin-shaped structure is patterned to expose a top surface of the first source/drain layer.
    Type: Application
    Filed: June 15, 2015
    Publication date: December 15, 2016
    Inventors: Chee Wee Liu, Samuel C. Pan, I-Hsieh Wong, Hung-Yu Yeh
  • Three-Dimensional Transistor and Methods of Manufacturing Thereof
    Publication number: 20160358940
    Abstract: Three-dimensional (3D) transistors and methods of manufacturing thereof include a first semiconductor fin extending over a substrate. The first semiconductor fin has a vertical recess extending from a first sidewall of the first semiconductor fin toward a second sidewall of the first semiconductor fin opposite the first sidewall. A distance between two opposing sidewalls of the vertical recess decreases as the vertical recess extends toward the second sidewall of the first semiconductor fin. The device further includes a vertically recessed channel region between the second sidewall of the first semiconductor fin and a bottom of the vertical recess, source/drain (S/D) regions at opposite ends of the vertically recessed channel region, and a gate stack over the vertically recessed channel region.
    Type: Application
    Filed: June 5, 2015
    Publication date: December 8, 2016
    Inventors: Jhih-Yang Yan, Samuel C. Pan, Chee Wee Liu, Hung-Yu Yeh, Da-Zhi Zhang
  • Transistor with Wurtzite Channel
    Publication number: 20160336389
    Abstract: A device includes a source region, a drain region, and a wurtzite semiconductor between the source region and the drain region. A source-drain direction is parallel to a [01-10] direction or a [?2110] direction of the wurtzite semiconductor. The device further includes a gate dielectric over the wurtzite semiconductor, and a gate electrode over the gate dielectric.
    Type: Application
    Filed: July 27, 2016
    Publication date: November 17, 2016
    Inventors: Hung-Chih Chang, Pin-Shiang Chen, Chee-Wee Liu, Samuel C. Pan
  • SEMICONDUCTOR DEVICE AND TRANSISTOR
    Publication number: 20160336312
    Abstract: This disclosure provides a negative capacitance gate stack structure with a variable positive capacitor to implement a hysteresis free negative capacitance field effect transistors (NCFETs) with improved voltage gain. The gate stack structure provides an effective ferroelectric negative capacitor by using the combination of a ferroelectric negative capacitor and the variable positive capacitor with semiconductor material (such as polysilicon), resulting in the effective ferroelectric negative capacitor's being varied with an applied gate voltage. Our simulation results show that the NCFET with the variable positive capacitor can achieve not only a non-hysteretic ID-VG curve but also a better sub-threshold slope.
    Type: Application
    Filed: May 15, 2015
    Publication date: November 17, 2016
    Inventors: JHIH-YANG YAN, CHEE-WEE LIU, DER-CHUAN LAI
  • Field effect transistors and methods of forming same
    Patent number: 9490430
    Abstract: Semiconductor devices and methods of forming the same are provided. A first gate electrode layer is formed over a substrate. A first gate dielectric layer is formed over the first gate electrode layer. A first channel layer is formed over the first gate dielectric layer. An isolation layer is formed over the first channel layer. A second channel layer is formed over the isolation layer. A second gate dielectric layer is formed over the second channel layer. The second gate dielectric layer, the second channel layer, the isolation layer and the first channel layer are patterned to form a first opening, the first opening extending through the first gate dielectric layer, the second channel layer and the isolation layer, and into the first channel layer. A first source/drain region is formed in the first opening.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: November 8, 2016
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Taiwan University
    Inventors: Pin-Shiang Chen, Samuel C. Pan, Chee-Wee Liu, Sheng-Ting Fan
  • Semiconductor Devices and Manufacturing Methods Thereof
    Publication number: 20160307928
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a first fin field effect transistor (FinFET) disposed over a substrate, and a second FinFET device disposed over the first FinFET. A junction isolation material is disposed between a source of the first FinFET and a source of the second FinFET.
    Type: Application
    Filed: June 29, 2016
    Publication date: October 20, 2016
    Inventors: Chee-Wee Liu, Hung-Chih Chang, Cheng-Yi Peng, Chih-Sheng Chang
  • Transistor with wurtzite channel
    Patent number: 9425250
    Abstract: A device includes a source region, a drain region, and a wurtzite semiconductor between the source region and the drain region. A source-drain direction is parallel to a [01-10] direction or a [?2110] direction of the wurtzite semiconductor. The device further includes a gate dielectric over the wurtzite semiconductor, and a gate electrode over the gate dielectric.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: August 23, 2016
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Taiwan University
    Inventors: Hung-Chih Chang, Pin-Shiang Chen, Chee-Wee Liu, Samuel C. Pan
  • Semiconductor devices and manufacturing methods thereof
    Patent number: 9406697
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a first fin field effect transistor (FinFET) disposed over a substrate, and a second FinFET device disposed over the first FinFET. A junction isolation material is disposed between a source of the first FinFET and a source of the second FinFET.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: August 2, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chee-Wee Liu, Hung-Chih Chang, Cheng-Yi Peng, Chih-Sheng Chang
  • Semiconductor Devices and Manufacturing Methods Thereof
    Publication number: 20160211276
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a first fin field effect transistor (FinFET) disposed over a substrate, and a second FinFET device disposed over the first FinFET. A junction isolation material is disposed between a source of the first FinFET and a source of the second FinFET.
    Type: Application
    Filed: January 20, 2015
    Publication date: July 21, 2016
    Inventors: Chee-Wee Liu, Hung-Chih Chang, Cheng-Yi Peng, Chih-Sheng Chang