Patents by Inventor Chee Yang Ng
Chee Yang Ng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240150699Abstract: An electroporation system including one or more of a pipette, a pipette tip, a pipette docking assembly, and a pulse generator. The pipette docking assembly includes a pipette station, a pipette station guard, and a reservoir (e.g., a buffer tube). A method for transfecting a cell with a payload including providing an electroporation system, providing the cell, providing the payload, introducing the cell and the payload into a pipette tip, and electroporating the cell within the pipette tip by operating the electroporation system.Type: ApplicationFiled: September 15, 2023Publication date: May 9, 2024Inventors: Han WEI, Chee Wai CHAN, Wui Khen LIAW, Shan Hua DONG, See Chen GOH, Huei Steven YEO, Harmon Cosme SICAT, JR., Mio Xiu Lu LING, Josh M. MEAD, Mikko MAKINEN, Beng Heng LIM, Kuan Moon BOO, Justina Linkai BONG, Chye Sin NG, Wee Liam LIM, Li Yang LIM, Way Xuang LEE
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Publication number: 20230371165Abstract: A voltage regulator module includes: power input and output terminals at a same side of the voltage regulator module; a first power stage configured to receive an input voltage from the power input terminal and output a phase current at a switch node of the first power stage, the first power stage including an inductor having a vertical conductor embedded in a magnetic core, the vertical conductor having a first end which is electrically connected to the switch node and a second end opposite the first end; and a first metal clip which electrically connects the second end of the vertical conductor to the power output terminal such that power is delivered to and from the voltage regulator module at the same side of the voltage regulator module. A method of producing the voltage regulator module and electronic assembly that includes the voltage regulator module are also described.Type: ApplicationFiled: May 12, 2022Publication date: November 16, 2023Inventors: Gerald Deboy, Kok Yau Chua, Angela Kessler, Kennith Kin Leong, Chee Yang Ng, Luca Peluso
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Publication number: 20230335516Abstract: A method of manufacturing a package is disclosed. In one example, the method comprises applying a metallic connection structure, which comprises a solder or sinter material, on a sacrificial carrier. An electronic component is mounted on the metallic connection structure. At least part of the electronic component and of the metallic connection structure is encapsulated. Thereafter, the sacrificial carrier is removed to thereby expose at least part of the metallic connection structure.Type: ApplicationFiled: March 23, 2023Publication date: October 19, 2023Applicant: Infineon Technologies AGInventors: Chee Yang NG, Chew Yeek LAU, Swee Kah LEE, Joseph Victor SOOSAI PRAKASAM, Hui Khin TAN
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Patent number: 11676879Abstract: A semiconductor package includes: a carrier having a first side and a second side opposite the first side, the first side having a plurality of contact structures; a semiconductor die having a first side and a second side opposite the first side, the first side of the semiconductor die having a plurality of pads attached to the plurality of contact structures at the first side of the carrier; a metal plate attached to the second side of the semiconductor die, the metal plate having a size that is independent of the size of the carrier and based on an expected thermal load to be presented by the semiconductor die; and an encapsulant confined by the carrier and the metal plate and laterally surrounding an edge of the semiconductor die. Corresponding methods of production are also provided.Type: GrantFiled: September 28, 2020Date of Patent: June 13, 2023Assignee: Infineon Technologies AGInventors: Stefan Woetzel, Chee Yang Ng
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Publication number: 20230052437Abstract: A method of producing a semiconductor package includes providing a substrate formed of electrically insulating material and including a die mounting surface, and a first semiconductor die embedded within the substrate, the first semiconductor die including a first conductive terminal that faces the die mounting surface, providing a second semiconductor die that includes a first conductive terminal, and mounting the second semiconductor die on the die mounting surface such that the first conductive terminal of the second semiconductor die faces and is spaced apart from the die mounting surface, a first electrical connection that directly connects the first conductive terminals of the first and second semiconductor dies together is formed, and the second semiconductor die partially overlaps with the first semiconductor die.Type: ApplicationFiled: October 26, 2022Publication date: February 16, 2023Inventors: Stefan Woetzel, Chee Yang Ng
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Publication number: 20230027669Abstract: An electronic system is disclosed. In one example, the electronic system comprises an at least partially electrically conductive carrier, an electronic component, and an intermetallic connection structure connecting the carrier and the component. The intermetallic connection structure comprising an intermetallic mesh structure in a central portion of the intermetallic connection structure, and opposing exterior structures without intermetallic mesh and each arranged between the intermetallic mesh structure and the carrier or the component.Type: ApplicationFiled: July 25, 2022Publication date: January 26, 2023Applicant: Infineon Technologies AGInventors: Chee Yang NG, Edmund RIEDL, Joseph Victor SOOSAI PRAKASAM
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Patent number: 11521907Abstract: A semiconductor package includes a substrate formed of electrically insulating material and having a die mounting surface, a first semiconductor die embedded within the substrate and comprising a first conductive terminal that faces the die mounting surface, a second semiconductor die mounted on the die mounting surface and comprising a first conductive terminal that faces and is spaced apart from the die mounting surface, and a first electrical connection that directly connects the first conductive terminals of the first and second semiconductor dies together, wherein the second semiconductor die partially overlaps with the first semiconductor die.Type: GrantFiled: October 14, 2020Date of Patent: December 6, 2022Assignee: Infineon Technologies AGInventors: Stefan Woetzel, Chee Yang Ng
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Patent number: 11393743Abstract: A semiconductor device includes a conductive frame comprising a die attach surface that is substantially planar, a semiconductor die comprising a first load on a rear surface and a second terminal disposed on a main surface, a first conductive contact structure disposed on the die attach surface, and a second conductive contact structure on the main surface. The first conductive contact structure vertically extends past a plane of the main surface of the semiconductor die. The first conductive contact structure is electrically isolated from the main surface of the semiconductor die by an electrical isolation structure. An upper surface of the electrical isolation structure is below the main surface of the semiconductor die.Type: GrantFiled: December 18, 2019Date of Patent: July 19, 2022Assignee: Infineon Technologies AGInventors: Stuart Cardwell, Chee Yang Ng, Josef Maerz, Clive O'Dell, Mark Pavier
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Publication number: 20220139798Abstract: A method of forming a chip package is provided. The method may include: arranging an elastic thermal interface material over a semiconductor chip, wherein the elastic thermal interface material may be configured to transfer heat from the chip to an outside; arranging a mold around the thermal interface material and at least partially around the semiconductor chip, thereby compressing the elastic thermal interface material with the mold; and filling the mold with a packaging material.Type: ApplicationFiled: November 5, 2021Publication date: May 5, 2022Inventor: Chee Yang Ng
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Publication number: 20220122906Abstract: A package and method of manufacturing a package is disclosed. In one example, a package which comprises a first transistor chip having a first source pad and a second transistor chip having a second source pad and being stacked with the first transistor chip at an interface area. The first source pad and the second source pad are coupled at the interface area.Type: ApplicationFiled: September 27, 2021Publication date: April 21, 2022Applicant: Infineon Technologies AGInventors: Sergey YUFEREV, Paul Armand Asentista CALO, Theng Chao LONG, Josef MAERZ, Chee Yang NG, Petteri PALM, Wae Chet YONG
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Publication number: 20220115287Abstract: A semiconductor package includes a substrate formed of electrically insulating material and having a die mounting surface, a first semiconductor die embedded within the substrate and comprising a first conductive terminal that faces the die mounting surface, a second semiconductor die mounted on the die mounting surface and comprising a first conductive terminal that faces and is spaced apart from the die mounting surface, and a first electrical connection that directly connects the first conductive terminals of the first and second semiconductor dies together, wherein the second semiconductor die partially overlaps with the first semiconductor die.Type: ApplicationFiled: October 14, 2020Publication date: April 14, 2022Inventors: Stefan Woetzel, Chee Yang Ng
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Publication number: 20220102263Abstract: A semiconductor package includes: a carrier having an electrically insulative body and a first contact structure at a first side of the electrically insulative body; and a semiconductor die having a first pad attached to the first contact structure of the carrier, the first pad being at source or emitter potential. The first pad is spaced inward from an edge of the semiconductor die by a first distance. The semiconductor die has an edge termination region between the edge and the first pad. The first contact structure of the carrier is spaced inward from the edge of the semiconductor die by a second distance greater than the first distance such that an electric field that emanates from the edge termination region in a direction of the carrier during normal operation of the semiconductor die does not reach the first contact structure of the carrier. Methods of production are also provided.Type: ApplicationFiled: August 27, 2021Publication date: March 31, 2022Inventors: Chee Yang Ng, Stefan Woetzel, Edward Fuergut, Thai Kee Gan, Chee Hong Lee, Jayaganasan Narayanasamy, Ralf Otremba
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Publication number: 20220102235Abstract: A semiconductor package includes: a carrier having a first side and a second side opposite the first side, the first side having a plurality of contact structures; a semiconductor die having a first side and a second side opposite the first side, the first side of the semiconductor die having a plurality of pads attached to the plurality of contact structures at the first side of the carrier; a metal plate attached to the second side of the semiconductor die, the metal plate having a size that is independent of the size of the carrier and based on an expected thermal load to be presented by the semiconductor die; and an encapsulant confined by the carrier and the metal plate and laterally surrounding an edge of the semiconductor die. Corresponding methods of production are also provided.Type: ApplicationFiled: September 28, 2020Publication date: March 31, 2022Inventors: Stefan Woetzel, Chee Yang Ng
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Patent number: 11289436Abstract: Embodiments of molded packages and corresponding methods of manufacture are provided. In an embodiment of a molded package, the molded package includes a laser-activatable mold compound having a plurality of laser-activated regions which are plated with an electrically conductive material to form metal pads and/or metal traces at a first side of the laser-activatable mold compound. A semiconductor die embedded in the laser-activatable mold compound has a plurality of die pads. An interconnect electrically connects the plurality of die pads of the semiconductor die to the metal pads and/or metal traces at the first side of the laser-activatable mold compound.Type: GrantFiled: May 28, 2020Date of Patent: March 29, 2022Assignee: Infineon Technologies Austria AGInventors: Chee Hong Lee, Kok Yau Chua, Chii Shang Hong, Swee Kah Lee, Chee Yang Ng, Klaus Schiess
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Patent number: 11174152Abstract: An embodiment device includes a body structure having an interior cavity, a control chip disposed on a first interior surface of the interior cavity, and a sensor attached, at a first side, to a second interior surface of the interior cavity opposite the first interior surface. The sensor has a mounting pad on a second side of the sensor that faces the first interior surface, and the sensor is vertically spaced apart from the control chip by an air gap, with the sensor is aligned at least partially over the control chip. The device further includes an interconnect having a first end mounted on the mounting pad, the interconnect extending through the interior cavity toward the first interior surface, and the control chip is in electrical communication with the sensor by way of the interconnect.Type: GrantFiled: October 22, 2019Date of Patent: November 16, 2021Assignee: INFINEON TECHNOLOGIES AGInventors: Sook Woon Chan, Chau Fatt Chiang, Kok Yau Chua, Swee Kah Lee, Chee Yang Ng
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Publication number: 20210193560Abstract: A semiconductor device includes a conductive frame comprising a die attach surface that is substantially planar, a semiconductor die comprising a first load on a rear surface and a second terminal disposed on a main surface, a first conductive contact structure disposed on the die attach surface, and a second conductive contact structure on the main surface. The first conductive contact structure vertically extends past a plane of the main surface of the semiconductor die. The first conductive contact structure is electrically isolated from the main surface of the semiconductor die by an electrical isolation structure. An upper surface of the electrical isolation structure is below the main surface of the semiconductor die.Type: ApplicationFiled: December 18, 2019Publication date: June 24, 2021Inventors: Stuart Cardwell, Chee Yang Ng, Josef Maerz, Clive O'Dell, Mark Pavier
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Patent number: 11039231Abstract: In accordance with an embodiment a package includes: a package structure which defines inner surfaces delimiting an inner volume and outer surfaces directed towards an exterior of the package; at least one acoustic sensor element applied to at least one of the inner surfaces, to convert acoustic waves arriving from the exterior of the package into acoustic information in the form of electric signals; a plurality of millimeter wave sensing elements applied to at least one of the outer surfaces, to receive reflected radar signals from objects in the exterior of the package; and a circuitry applied to at least one of the inner surfaces of the package structure, wherein the circuitry is electrically connected to the at least one acoustic sensor element and the plurality of millimeter wave sensing elements to process the acoustic information and the reflected radar signals.Type: GrantFiled: November 13, 2019Date of Patent: June 15, 2021Assignee: INFINEON TECHNOLOGIES AGInventors: Kok Yau Chua, Chee Yang Ng
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Publication number: 20200381380Abstract: Embodiments of molded packages and corresponding methods of manufacture are provided. In an embodiment of a molded package, the molded package includes a laser-activatable mold compound having a plurality of laser-activated regions which are plated with an electrically conductive material to form metal pads and/or metal traces at a first side of the laser-activatable mold compound. A semiconductor die embedded in the laser-activatable mold compound has a plurality of die pads. An interconnect electrically connects the plurality of die pads of the semiconductor die to the metal pads and/or metal traces at the first side of the laser-activatable mold compound.Type: ApplicationFiled: May 28, 2020Publication date: December 3, 2020Inventors: Chee Hong Lee, Kok Yau Chua, Chii Shang Hong, Swee Kah Lee, Chee Yang Ng, Klaus Schiess
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Patent number: 10770399Abstract: A semiconductor package includes a frame having an insulative body with a first main surface and a second main surface opposite the first main surface, a first plurality of metal traces at the first main surface, and a first cavity in the insulative body. A thermally and/or electrically conductive material filling the first cavity in the insulative body and having a different composition than the first plurality of metal traces. The thermally and/or electrically conductive material provides a thermally and/or electrically conductive path between the first and the second main surfaces of the insulative body. A semiconductor die attached to the frame at the first main surface of the insulative body is electrically connected to the first plurality of metal traces and to the thermally and/or electrically conductive material filling the first cavity in the insulative body. A corresponding method of manufacture is also described.Type: GrantFiled: February 13, 2019Date of Patent: September 8, 2020Assignee: Infineon Technologies AGInventors: Chee Yang Ng, Hock Siang Chua, Stefan Macheiner, Josef Maerz, Nurfarena Othman, Joseph Victor Soosai Prakasam, Hong Hock Tay
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Publication number: 20200258842Abstract: A semiconductor package includes a frame having an insulative body with a first main surface and a second main surface opposite the first main surface, a first plurality of metal traces at the first main surface, and a first cavity in the insulative body. A thermally and/or electrically conductive material filling the first cavity in the insulative body and having a different composition than the first plurality of metal traces. The thermally and/or electrically conductive material provides a thermally and/or electrically conductive path between the first and the second main surfaces of the insulative body. A semiconductor die attached to the frame at the first main surface of the insulative body is electrically connected to the first plurality of metal traces and to the thermally and/or electrically conductive material filling the first cavity in the insulative body. A corresponding method of manufacture is also described.Type: ApplicationFiled: February 13, 2019Publication date: August 13, 2020Inventors: Chee Yang Ng, Hock Siang Chua, Stefan Macheiner, Josef Maerz, Nurfarena Othman, Joseph Victor Soosai Prakasam, Hong Hock Tay