Abstract: A package includes: a vertically extending first electronic component with at least one exposed electrically conductive first terminal; a vertically extending second electronic component with at least one exposed electrically conductive second terminal; and a clip with an accommodation volume in which the first electronic component and the second electronic component are accommodated and are held together. The at least one first terminal and the at least one second terminal are electrically accessible at a bottom of the clip.

Abstract: A method of manufacturing an electronic module assembly includes forming the electronic module assembly, wherein the electronic module assembly comprises a plurality of internal exposed surfaces, a plurality of external exposed surfaces, at least one internal cavity, and an internal heat source configured to generate heat internally within the electronic module assembly; dipping the electronic module assembly into a thermally conductive material to coat the plurality of internal exposed surfaces and the plurality of external exposed surfaces and to at least partially fill the at least one internal cavity; and curing the thermally conductive material formed on the plurality of internal exposed surfaces and the plurality of external exposed surfaces and filled within the at least one internal cavity to form a thermally conductive layer, wherein the thermally conductive layer is formed as a one-piece integral member.

Abstract: A method for fabricating one or more semiconductor packages includes: a substrate layer including one or more electrical contact regions; connecting a semiconductor die with one of the electrical contact regions; providing a heat dissipation member including one or more contact areas; attaching a tape to a backside of the heat dissipation member so that opposing ends of the tape extend beyond opposing side edges of the heat dissipation member; connecting a frontside of the heat dissipation member with the semiconductor die by coupling at least one contact area with the semiconductor die; placing a mold tool above the heat dissipation member and the substrate layer with the opposing ends of the tape extending out of the mold tool so that the tape is removable from outside the mold tool; filling an encapsulant into the mold cavity; and removing the tape.

Abstract: A power module includes: a power input terminal; a power output terminal at a same side of the power module as the power input terminal; a first power stage configured to receive an input voltage from the power input terminal and output a phase current at a switch node of the first power stage, the first power stage including an inductor that includes a conductor extending through a magnetic core, the conductor having a first end which is electrically connected to the switch node and a second end opposite the first end; and a first metal clip electrically connecting the second end of the conductor to the power output terminal such that power is delivered to and from the power module at the same side of the power module. A method of producing the power module and electronic assembly that includes the power module are also described.

Abstract: A method of forming a chip package is provided. The method may include: arranging an elastic thermal interface material over a semiconductor chip, the elastic thermal interface material being configured to transfer heat from the chip to an outside; arranging a mold around the elastic thermal interface material and at least partially around the semiconductor chip, thereby compressing the elastic thermal interface material with the mold; and filling the mold with a packaging material.

Abstract: A voltage regulator module includes: power input and output terminals at a same side of the voltage regulator module; a first power stage configured to receive an input voltage from the power input terminal and output a phase current at a switch node of the first power stage, the first power stage including an inductor having a vertical conductor embedded in a magnetic core, the vertical conductor having a first end which is electrically connected to the switch node and a second end opposite the first end; and a first metal clip which electrically connects the second end of the vertical conductor to the power output terminal such that power is delivered to and from the voltage regulator module at the same side of the voltage regulator module. A method of producing the voltage regulator module and electronic assembly that includes the voltage regulator module are also described.

Abstract: A method of forming a chip package is provided. The method may include: arranging an elastic thermal interface material over a semiconductor chip, wherein the elastic thermal interface material may be configured to transfer heat from the chip to an outside; arranging a mold around the thermal interface material and at least partially around the semiconductor chip, thereby compressing the elastic thermal interface material with the mold; and filling the mold with a packaging material.

Abstract: A package and method of manufacturing a package is disclosed. In one example, a package which comprises a first transistor chip having a first source pad and a second transistor chip having a second source pad and being stacked with the first transistor chip at an interface area. The first source pad and the second source pad are coupled at the interface area.

Abstract: A solder structure and method is disclosed. In one example, the solder structure includes a solder material, and a coating which at least partially coats the solder material and is configured for protecting the solder material against solder spreading. The coating is at least partially disrupted when establishing a solder connection between the solder material and a solderable structure.

Abstract: A method of manufacturing an electronic module assembly includes forming the electronic module assembly, wherein the electronic module assembly comprises a plurality of internal exposed surfaces, a plurality of external exposed surfaces, at least one internal cavity, and an internal heat source configured to generate heat internally within the electronic module assembly; dipping the electronic module assembly into a thermally conductive material to coat the plurality of internal exposed surfaces and the plurality of external exposed surfaces and to at least partially fill the at least one internal cavity; and curing the thermally conductive material formed on the plurality of internal exposed surfaces and the plurality of external exposed surfaces and filled within the at least one internal cavity to form a thermally conductive layer, wherein the thermally conductive layer is formed as a one-piece integral member.

Abstract: A transistor package includes a power transistor chip having first and second opposite sides. The first side has source, drain, and gate electrode metallizations. A multi-layer laminate substrate includes: a first structured metal layer facing the first side of the chip and electrically connected to the source electrode metallization, the drain electrode metallization, and the gate electrode metallization; a second structured metal layer having a source package terminal pad, a source sense package terminal pad, a drain package terminal pad, and a gate package terminal pad; at least one insulating layer between the structured metal layers; and vias running through the insulating layer and connecting segments of the first structured metal layer to the terminal pads of the second structured metal layer.

Abstract: A semiconductor package includes: a carrier having an electrically insulative body and a first contact structure at a first side of the electrically insulative body; and a semiconductor die having a first pad attached to the first contact structure of the carrier, the first pad being at source or emitter potential. The first pad is spaced inward from an edge of the semiconductor die by a first distance. The semiconductor die has an edge termination region between the edge and the first pad. The first contact structure of the carrier is spaced inward from the edge of the semiconductor die by a second distance greater than the first distance such that an electric field that emanates from the edge termination region in a direction of the carrier during normal operation of the semiconductor die does not reach the first contact structure of the carrier. Methods of production are also provided.

Abstract: A voltage regulator module includes: power input and output terminals at a same side of the voltage regulator module; a first power stage configured to receive an input voltage from the power input terminal and output a phase current at a switch node of the first power stage, the first power stage including an inductor having a vertical conductor embedded in a magnetic core, the vertical conductor having a first end which is electrically connected to the switch node and a second end opposite the first end; and a first metal clip which electrically connects the second end of the vertical conductor to the power output terminal such that power is delivered to and from the voltage regulator module at the same side of the voltage regulator module. A method of producing the voltage regulator module and electronic assembly that includes the voltage regulator module are also described.

Abstract: A method of manufacturing a package is disclosed. In one example, the method comprises applying a metallic connection structure, which comprises a solder or sinter material, on a sacrificial carrier. An electronic component is mounted on the metallic connection structure. At least part of the electronic component and of the metallic connection structure is encapsulated. Thereafter, the sacrificial carrier is removed to thereby expose at least part of the metallic connection structure.

Abstract: A semiconductor package includes: a carrier having a first side and a second side opposite the first side, the first side having a plurality of contact structures; a semiconductor die having a first side and a second side opposite the first side, the first side of the semiconductor die having a plurality of pads attached to the plurality of contact structures at the first side of the carrier; a metal plate attached to the second side of the semiconductor die, the metal plate having a size that is independent of the size of the carrier and based on an expected thermal load to be presented by the semiconductor die; and an encapsulant confined by the carrier and the metal plate and laterally surrounding an edge of the semiconductor die. Corresponding methods of production are also provided.

Abstract: A method of producing a semiconductor package includes providing a substrate formed of electrically insulating material and including a die mounting surface, and a first semiconductor die embedded within the substrate, the first semiconductor die including a first conductive terminal that faces the die mounting surface, providing a second semiconductor die that includes a first conductive terminal, and mounting the second semiconductor die on the die mounting surface such that the first conductive terminal of the second semiconductor die faces and is spaced apart from the die mounting surface, a first electrical connection that directly connects the first conductive terminals of the first and second semiconductor dies together is formed, and the second semiconductor die partially overlaps with the first semiconductor die.

Abstract: An electronic system is disclosed. In one example, the electronic system comprises an at least partially electrically conductive carrier, an electronic component, and an intermetallic connection structure connecting the carrier and the component. The intermetallic connection structure comprising an intermetallic mesh structure in a central portion of the intermetallic connection structure, and opposing exterior structures without intermetallic mesh and each arranged between the intermetallic mesh structure and the carrier or the component.

Abstract: A semiconductor package includes a substrate formed of electrically insulating material and having a die mounting surface, a first semiconductor die embedded within the substrate and comprising a first conductive terminal that faces the die mounting surface, a second semiconductor die mounted on the die mounting surface and comprising a first conductive terminal that faces and is spaced apart from the die mounting surface, and a first electrical connection that directly connects the first conductive terminals of the first and second semiconductor dies together, wherein the second semiconductor die partially overlaps with the first semiconductor die.

Abstract: A semiconductor device includes a conductive frame comprising a die attach surface that is substantially planar, a semiconductor die comprising a first load on a rear surface and a second terminal disposed on a main surface, a first conductive contact structure disposed on the die attach surface, and a second conductive contact structure on the main surface. The first conductive contact structure vertically extends past a plane of the main surface of the semiconductor die. The first conductive contact structure is electrically isolated from the main surface of the semiconductor die by an electrical isolation structure. An upper surface of the electrical isolation structure is below the main surface of the semiconductor die.

Abstract: A method of forming a chip package is provided. The method may include: arranging an elastic thermal interface material over a semiconductor chip, wherein the elastic thermal interface material may be configured to transfer heat from the chip to an outside; arranging a mold around the thermal interface material and at least partially around the semiconductor chip, thereby compressing the elastic thermal interface material with the mold; and filling the mold with a packaging material.