Patents by Inventor Chen An

Chen An has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150134275
    Abstract: Provided are a steam flow metering device and a metering method therefor. The device mainly comprises a mono-energetic gamma sensor (5), a Venturi-type flowmeter (6), a temperature transmitter (2), a pressure transmitter (3), a pipe connection section at the steam-inlet (1), and a pipe connection section at the steam-outlet (7), the function thereof being to measure the quantity of saturated water and saturated steam within the steam effectively and in real time.
    Type: Application
    Filed: January 16, 2012
    Publication date: May 14, 2015
    Inventors: Jige Chen, Yanzhi Pan, Guodong Wu, Zhiyong Wu
  • Publication number: 20150134980
    Abstract: A power supplying circuit adapted for receiving an output from a power adapter and supplying power to a battery unit and a system load is provided. The power supplying circuit includes a charger unit, a switching unit, and a voltage regulating unit. The charger unit receives a first supplying voltage from the power adapter through a power terminal and charges the battery unit. The switching unit is coupled to the power terminal and the charger unit. The switch unit is configured for receiving the first supplying voltage and a second supplying voltage from the charger unit. The voltage regulating unit is coupled to the switching unit and configured for powering the system load. The switching unit supplies the first supplying voltage to the voltage regulating unit under heavy load condition. The switching unit supplies the second supplying voltage to the voltage regulating unit under light load condition.
    Type: Application
    Filed: April 4, 2014
    Publication date: May 14, 2015
    Applicant: Wistron Corp.
    Inventors: CHIEN-LIANG CHEN, CHIEN-FU LIAO
  • Publication number: 20150129294
    Abstract: A wiring seat includes an insulative base and a connecting member. The insulative base has a fixing hole and an engagement hole or a through hole beside the fixing hole. The connecting member has a conductive body. The conductive body is bendingly extended with a positioning sheet engaging with the engagement hole or a terminal pin passing the through hole. The conductive body has a passing hole corresponding to the fixing hole.
    Type: Application
    Filed: November 11, 2013
    Publication date: May 14, 2015
    Inventor: YU-SYUAN CHEN
  • Publication number: 20150130681
    Abstract: An antenna comprises a first layer having a first redistribution layer, a feeding line, a ground connection element, and one or more antenna inputs. The antenna also comprises one or more intermediate layers over the first layer. The antenna further comprises a second layer having a second redistribution layer over the one or more intermediate layers. The antenna additionally comprises one or more through vias arranged to communicatively couple the second redistribution layer and the first redistribution layer. The antenna also comprises a short element. The antenna further comprises one or more radiator antennas within the one or more through vias, the one or more radiator antennas being in communication with the one or more antenna inputs by way of the feeding line.
    Type: Application
    Filed: November 8, 2013
    Publication date: May 14, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jeng-Shieh HSIEH, Chung-Hao TSAI, Chuei-Tang WANG, Chen-Hua YU
  • Publication number: 20150131329
    Abstract: An apparatus comprises a bridge coupled between a bias voltage and ground, wherein the bridge comprises a first switch and a second switch connected in series and coupled between the bias voltage and ground and a third switch and a fourth switch connected in series and coupled between the bias voltage and ground, a resonant device coupled to the bridge, wherein the resonant device comprises a fixed capacitance, a gate capacitance and a magnetizing inductance, a transformer coupled to the resonant device, wherein the transformer comprises a primary winding and a plurality of secondary windings.
    Type: Application
    Filed: November 12, 2013
    Publication date: May 14, 2015
    Applicant: FutureWei Technologies, Inc.
    Inventors: Daoshen Chen, Heping Dai, Xujun Liu, Liming Ye, Dianbo Fu
  • Publication number: 20150132971
    Abstract: One or more plasma etching techniques are provided. Selective plasma etching is achieved by introducing a gas into a chamber containing a photoresist over a substrate, establishing a bias at a frequency to convert the gas to a plasma at the frequency, and using the plasma to etch the photoresist. The frequency controls an electron density of the plasma and by maintaining a low electron density causes free radicals of the plasma to chemically etch the photoresist, rather than physically etching using ion bombardment. A mechanism is thus provided for chemically etching a photoresist under what are typically physical etching conditions.
    Type: Application
    Filed: November 13, 2013
    Publication date: May 14, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu Chao Lin, Chao-Cheng Chen
  • Publication number: 20150131457
    Abstract: A gain asymmetry characterizing circuit for determining characteristics of gain asymmetry possessed by a transmitter includes a baseband loopback path, a test signal generating unit and a gain asymmetry measuring unit. The baseband loopback path is coupled to a baseband node on a first transmission path of the transmitter. The test signal generating unit is arranged to generate a first differential baseband test signal pair to the first transmission path. The first differential baseband test signal pair includes a first baseband signal and a second baseband signal. During a first period, the first baseband signal and the second baseband signal are fed into a positive input node and a negative input node of the first transmission path, respectively. During a second period, the second baseband signal and the first baseband signal are fed into the positive input node and the negative input node of the first transmission path, respectively.
    Type: Application
    Filed: November 4, 2014
    Publication date: May 14, 2015
    Inventors: Neric Fong, Bing Xu, Wei-Cheng Liu, Terry W Chen
  • Publication number: 20150131237
    Abstract: A foldable package structure including a first substrate, a second substrate, a plurality of adhesive layers and at least one environmental-sensitive electronic component is provided. At least one of the first and second laminated substrates comprises an ultra-thin glass plate. The foldable package structure comprises a predetermined folded region and the ultra-thin glass plate is disposed at one side of the predetermined folded region and stays away from the predetermined folded region.
    Type: Application
    Filed: October 30, 2014
    Publication date: May 14, 2015
    Inventors: Kuang-Jung Chen, Cheng-Chung Lee
  • Publication number: 20150131711
    Abstract: An apparatus comprises a plurality of delay elements connected in series. Each delay element is configured to delay a respective input signal and to output a respective delayed signal. The apparatus also comprises a weight generator configured to generate a plurality of tap weights based on the delayed signals. The apparatus further comprises a tap controller configured to (1) generate tap weight enabling signals corresponding to one or more of the tap weights based on a determination that the corresponding tap weights are greater than a predetermined threshold value, and (2) generate a set of bias factors. The apparatus additionally comprises a summer configured to output a weighted signal based on the delayed signals, the tap weight enabling signals, the tap weights, and the bias factors.
    Type: Application
    Filed: January 22, 2015
    Publication date: May 14, 2015
    Inventors: Ming-Chieh HUANG, Jing Jing CHEN, Chan-Hong CHERN, Tao Wen CHUNG, Chih-Chang LIN, Yuwen SWEI
  • Publication number: 20150130014
    Abstract: The present disclosure provides a rectifier. The rectifier includes a N-type epitaxial layer, a plurality of P-type diffusion regions and a plurality of N-type diffusion regions. The P-type diffusion regions are disposed in the N-type epitaxial layer, and the N-type diffusion regions are respectively disposed in the P-type diffusion regions. Wherein, the P-type diffusion regions are electronically coupled to the N-type diffusion regions.
    Type: Application
    Filed: November 8, 2013
    Publication date: May 14, 2015
    Applicant: SUMPRO ELECTRONICS CORPORATION
    Inventor: Wei-Fan Chen
  • Publication number: 20150130518
    Abstract: An apparatus comprises a code generator configured to generate a coarse tuning signal and a reset signal based on a reference frequency and a phase difference signal. The apparatus also comprises a digital loop filter configured to generate a fine tuning signal based on the phase difference signal. The apparatus further comprises a voltage control oscillator configured to generate an output signal based on the coarse tuning signal and the fine tuning signal. The apparatus additionally comprises a divider configured to generate a divider frequency based on a divider control signal and the output signal. The phase difference signal is based, at least in part, on the divider frequency, and the divider is configured to be reset based on the reset signal.
    Type: Application
    Filed: January 23, 2015
    Publication date: May 14, 2015
    Inventors: Yen-Jen CHEN, Feng Wei KUO, Huan-Neng CHEN, Chewn-Pu JOU
  • Publication number: 20150129025
    Abstract: A HIT solar cell is provided, including a p-type crystalline silicon substrate having a light-receiving surface, a first intrinsic amorphous silicon thin-film layer formed on the light-receiving surface of the p-type crystalline silicon substrate, an n-type amorphous oxide layer formed on the first intrinsic amorphous silicon thin-film layer, and a first transparent conductive layer formed on the n-type amorphous oxide layer. In the HIT solar cell, the n-type amorphous oxide layer can be directly formed, without forming the first intrinsic amorphous silicon thin-film layer, and the n-type amorphous oxide layer can be divided into an n?-type amorphous oxide layer and an n+-type amorphous oxide layer that are formed sequentially.
    Type: Application
    Filed: January 24, 2014
    Publication date: May 14, 2015
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yu-Hung CHEN, Jun-Chin LIU, Yung-Tsung LIU, Chen-Cheng LIN
  • Publication number: 20150129827
    Abstract: Provided is a three-dimensional resistance memory including a stack of layers. The stack of layers is encapsulated in a dielectric layer and is adjacent to at least one opening in the encapsulating dielectric layer. At least one L-shaped variable resistance spacer is disposed on at least a portion of the sidewall of the opening adjacent to the stack of layers. An electrode layer fills the remaining portion of the opening.
    Type: Application
    Filed: September 17, 2014
    Publication date: May 14, 2015
    Inventors: Frederick T. Chen, Tai-Yuan Wu, Yu-Sheng Chen, Wei-Su Chen, Pei-Yi Gu, Yu-De Lin
  • Publication number: 20150134663
    Abstract: According to an embodiment, a candidate node having a potential association relationship with a target node, an association node having an association relationship with the target node, and a grouping identifier of the association node are obtained. A relevance degree between the association node and the target node and a relevance degree between the candidate node and the target node within each grouping identifier are obtained. Based on the relevance degrees, the association node and the candidate node in each grouping identifier are combined for outputting.
    Type: Application
    Filed: January 28, 2013
    Publication date: May 14, 2015
    Applicant: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Yuewen Liu, Chuan Chen, Peng He, Junming Mai, Yuhuang Li, Weihua Chen
  • Publication number: 20150133287
    Abstract: An exhaust gas reduction catalyst that exhibits high nitrogen oxide reduction performance, and a simple and efficient method for producing the catalyst, in which the amount of the waste liquid is reduced, further, an object of the invention is to provide a zeolite-containing catalyst for reducing nitrogen oxides, which does not use an expensive noble metal or the like and which has high nitrogen oxide reduction performance.
    Type: Application
    Filed: January 21, 2015
    Publication date: May 14, 2015
    Applicant: Mitsubishi Plastics, Inc.
    Inventors: Takeshi MATSUO, Takahiko Takewaki, Daisuke Nishioka, Kazunori Oshima, Haijun Chen, Hiroyuki Kakiuchi
  • Publication number: 20150129414
    Abstract: A physical vapor deposition (PVD) chamber, a process kit of a PVD chamber and a method of fabricating a process kit of a PVD chamber are provided. In various embodiments, the PVD chamber includes a sputtering target, a power supply, a process kit, and a substrate support. The sputtering target has a sputtering surface that is in contact with a process region. The power supply is electrically connected to the sputtering target. The process kit has an inner surface at least partially enclosing the process region, and a liner layer disposed on the inner surface. The substrate support has a substrate receiving surface, wherein the liner layer disposed on the inner surface of the process kit has a surface roughness (Rz), and the surface roughness (Rz) is substantially in a range of 50-200 ?m.
    Type: Application
    Filed: November 14, 2013
    Publication date: May 14, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Wei BIH, Wei-Jen CHEN, Yen-Yu CHEN, Hsien-Chieh HSIAO, Chang-Sheng LEE, Wei-Chen LIAO, Wei ZHANG
  • Publication number: 20150130050
    Abstract: A package includes a package substrate, which includes a middle layer selected from the group consisting of a core and a middle metal layer, a top metal layer overlying the middle layer, and a bottom metal layer underlying the middle layer. All metal layers overlying the middle layer have a first total metal density that is equal to a sum of all densities of all metal layers over the middle layer. All metal layers underlying the middle layer have a second total metal density that is equal to a sum of all densities of all metal layers under the middle layer. An absolute value of a difference between the first total metal density and the second total metal density is lower than about 0.1.
    Type: Application
    Filed: November 14, 2013
    Publication date: May 14, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Wei Lin, Guan-Yu Chen, Yu-Min Liang, Tin-Hao Kuo, Chen-Shien Chen
  • Publication number: 20150129795
    Abstract: The present disclosure relates to a chemical mechanical polishing (CMP) slurry composition that provides for a high metal to dielectric material selectivity along with a low rate of metal recess formation. In some embodiments, the disclosed slurry composition has an oxidant and an etching inhibitor. The oxidant has a compound with one or more oxygen molecules. The etching inhibitor has a nitrogen-oxide compound. The etching inhibitor reduces the rate of metal and dielectric material (e.g., oxide) removal, but does so in a manner that reduces the rate of dielectric material removal by a larger amount, so as to provide the slurry composition with a high metal (e.g., germanium) to dielectric material removal selectivity and with a low rate of metal recess formation.
    Type: Application
    Filed: November 13, 2013
    Publication date: May 14, 2015
    Inventors: Chia-Jung Hsu, Yun-Lung Ho, Neng-Kuo Chen, Wen-Feng Chueh, Sey-Ping Sun, Song-Yuan Chang
  • Publication number: 20150130629
    Abstract: An asset tag for monitoring usage of an electronic asset includes a usage monitor configured to monitor usage of the electronic asset and a transmitter configured to transmit an indication of the usage of the electronic asset. The asset tag may include a socket configured to receive a first plug, wherein the first plug comprises a plug of the electronic asset; a second plug electrically coupled to the socket, wherein the second plug is configured to transmit current to the socket; and, a power source configured to power the usage detector.
    Type: Application
    Filed: May 29, 2014
    Publication date: May 14, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: An Mei Chen, Robert Morris Morandy, Vijaya Datta Mayyuri, Jangwon Lee, Paul David Milne
  • Publication number: 20150133841
    Abstract: A posture loop includes an elastic band or cable having two end portions, a retainer bridge having a bar, the elastic cable includes an intermediate portion engaged with one end portion of the bar, and the end portions of the elastic cable are engaged with the other end portion of the bar, and two buckle members are attached to the end portions of the elastic cable for adjustably coupling the end portions of the elastic cable to the other end portion of the bar and for forming an eight (8)-shaped structure for the posture loop and for engaging onto shoulder portions of a user, The buckle members each include two grooves formed by a rib for engaging with the end portions of the elastic cable respectively.
    Type: Application
    Filed: November 14, 2013
    Publication date: May 14, 2015
    Inventor: Paul CHEN