Patents by Inventor Chen An

Chen An has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140273406
    Abstract: Systems, chambers, and processes are provided for controlling process defects caused by moisture contamination. The systems may provide configurations for chambers to perform multiple operations in a vacuum or controlled environment. The chambers may include configurations to provide additional processing capabilities in combination chamber designs. The methods may provide for the limiting, prevention, and correction of aging defects that may be caused as a result of etching processes performed by system tools.
    Type: Application
    Filed: April 8, 2014
    Publication date: September 18, 2014
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Anchuan Wang, Xinglong Chen, Zihui Li, Hiroshi Hamana, Zhijun Chen, Ching-Mei Hsu, Jiayin Huang, Nitin K. Ingle, Dmitry Lubomirsky, Shankar Venkataraman, Randhir Thakur
  • Publication number: 20140283041
    Abstract: An embodiment of the present application provides technologies for detecting malicious content embedded in a content downloaded from an external source. The downloaded content converted into an opcode sequence by a web browser in a computing device. The opcode sequence is compared with a pre-stored opcode signature. The opcode signature comprises multiple sentences, and each sentence has multiple clauses. Each clause may include a matching opcode, a condition, an instruction, and an identifier. When a matching opcode in a clause matches with an opcode of the opcode sequence, and the condition as specified in the clause is determined to be true, the instruction in the clause is taken and next sentence identified by the identifier is taken to match the opcode sequence. Eventually, the last taken clause in the opcode signature may instruct whether opcode sequence contains malicious code.
    Type: Application
    Filed: March 13, 2014
    Publication date: September 18, 2014
    Applicant: HUAWEI TECHNOLOGIES CO.,LTD.
    Inventors: YINZHI CAO, XIANG PAN, YAN CHEN, JIANWEI ZHUGE, XIAOBIN QIAN, JIAN FU
  • Publication number: 20140264236
    Abstract: Provision of fabrication, construction, and/or assembly of a memory device including a two-terminal memory portion is described herein. The two-terminal memory device fabrication can provide enhanced capabilities in connection with precisely tuning on-state current over a greater possible range.
    Type: Application
    Filed: June 5, 2013
    Publication date: September 18, 2014
    Inventors: Kuk-Hwan KIM, Ping LU, Chen-Chun CHEN, Sung Hyun JO
  • Publication number: 20140266112
    Abstract: One embodiment includes a power regulator system. The system includes a switch control stage configured to generate at least one activation signal based on a pulse-width modulation (PWM) signal and to control a respective at least one switch to generate an output voltage. The system also includes a feedback stage configured to generate the PWM signal based on a ramp signal and a feedback voltage that is based on the output voltage. The system further includes a ramp generator stage configured to adaptively generate the ramp signal based on the output voltage and based on the at least one activation signal.
    Type: Application
    Filed: May 31, 2013
    Publication date: September 18, 2014
    Inventors: KUANG-YAO CHENG, HAL CHEN, WENKAI WU, WEIDONG ZHU
  • Publication number: 20140264463
    Abstract: The present disclosure provides one embodiment of a semiconductor structure that includes a first metal layer formed on a semiconductor substrate, wherein the first metal layer includes a first metal feature in a first region and a second metal feature in a second region; a second metal layer disposed on the first metal layer, wherein the second metal layer includes a third metal feature in the first region and a fourth metal feature in a second region; a magneto-resistive memory device sandwiched between the first metal feature and the third metal feature; and a capacitor sandwiched between the second metal feature and the fourth metal feature.
    Type: Application
    Filed: October 30, 2013
    Publication date: September 18, 2014
    Inventors: Chung-Cheng Chou, Ya-Chen Kao, Tien-Wei Chiang
  • Publication number: 20140264930
    Abstract: A method embodiment includes forming a sacrificial film layer over a top surface of a die, the die having a contact pad at the top surface. The die is attached to a carrier, and a molding compound is formed over the die and the sacrificial film layer. The molding compound extends along sidewalls of the die. The sacrificial film layer is exposed. The contact pad is exposed by removing at least a portion of the sacrificial film layer. A first polymer layer is formed over the die, and a redistribution layer (RDL) is formed over the die and electrically connects to the contact pad.
    Type: Application
    Filed: July 9, 2013
    Publication date: September 18, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Yen-Chang Hu, Ching-Wen Hsiao, Mirng-Ji Lii, Chung-Shi Liu, Chien Ling Hwang, Chih-Wei Lin, Chen-Shien Chen
  • Publication number: 20140272496
    Abstract: A micro-channel cooling fin for a battery module and battery is provided. The cooling fin includes a metal plate assembly that defines a plurality of cooling channels therein. The metal plate assembly includes an inlet section for introducing a coolant into the plurality of cooling channels and an outlet section from which the coolant exits the plurality of cooling channels. Each channel has an output temperature and an input temperature such that the output temperature minus the input temperature for each cooling channel is within a predetermined amount.
    Type: Application
    Filed: March 12, 2013
    Publication date: September 18, 2014
    Inventors: TAEYOUNG HAN, KUO-HUEY CHEN, BAHRAM KHALIGHI, RACHIT GARG, PHILIP KLAUS
  • Publication number: 20140278282
    Abstract: Downhole drilling tools designed and manufactured to reduce bit axial force and torque and to enhance drilling efficiency comprising laying out some cutters in one spiral direction of rotation about a bit rotational axis and other cutters in an opposite spiral direction of rotation; evaluating forces acting on cutters during simulated engagement with a downhole formation (straight and transitional drilling); and modifying cutter layout with respect to a spiral direction of rotation. Some embodiments further comprise, prior to simulation, placing cutters in cutter groups/sets at respective locations to obtain a level of force balance. Multilevel force balanced downhole drilling tools may be designed using five respective simulations: cutter group level, neighbor cutter group level, cutter set level, group of N (N=3 or N=4) consecutive cutters level and all cutters level. Cutter layout procedures and algorithms to minimize respective bit forces and in some embodiments to obtain force balance are described.
    Type: Application
    Filed: March 21, 2014
    Publication date: September 18, 2014
    Inventor: Shilin Chen
  • Publication number: 20140259658
    Abstract: A method includes patterning a layer over a substrate with a first metal pattern; using a cut mask in a first position relative to the substrate to perform a first cut patterning for removing material from a first region within the first pattern; and using the same cut mask to perform a second cut patterning while in a second position relative to the same layer over the substrate, for removing material from a second region in a second metal pattern of the same layer over the substrate.
    Type: Application
    Filed: June 24, 2013
    Publication date: September 18, 2014
    Inventors: Chin-Hsiung HSU, Huang-Yu CHEN, Tsong-Hua OU, Wen-Hao CHEN
  • Publication number: 20140265473
    Abstract: Disclosed is a car seat for protecting vertebral column, comprising: a backrest and a seat, wherein there is disposed with a troughed recess at a central portion of each of the backrest and the seat, so that when the backrest and the seat are subject to external impact, the impact damage incurred by the backrest and the seat onto a human vertebral column may be avoided, and in this way the human vertebral column can therefore be protected; in an embodiment of the present invention, there further comprises a plurality of viscous elastomers disposed inside the backrest and the seat, these viscous elastomers are set up in a corresponding arrangement on two sides of a human vertebral column, so as to assist in biasing the muscle on the two sides of the vertebral column to cause less direct impact by the external force, and to provide a cushioning effect.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: FORSOUND CORP.
    Inventor: Fu-Chieng CHEN
  • Publication number: 20140262083
    Abstract: An apparatus for raising and lowering a covering member of a window covering includes a sliding base, a first biasing device, a connecting device, and a second biasing device. The sliding base is moved between a first position and a second position in a headrail. The first biasing device has two first biasing members to urge the sliding base toward the first position. The connecting device is moved between a third position and a fourth position in the headrail. The second biasing device has a second biasing member to urge the connecting device toward the third position. The second biasing member of the second biasing device is added at a middle of raising the covering member to help the covering member totally received close to or in the headrail.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: NIEN MADE ENTERPRISE CO., LTD.
    Inventor: LIN CHEN
  • Publication number: 20140264234
    Abstract: A semiconductor structure includes a memory region. A memory structure is disposed on the memory region. The memory structure includes a first electrode, a resistance variable layer, a protection material and a second electrode. The first electrode has a top surface on the memory region. The resistance variable layer has at least a first portion and a second portion. The first portion is disposed over the top surface of the first electrode and the second portion extends upwardly from the first portion. The protection material surrounds the second portion of the resistance variable layer. The protection material is configurable to protect at least one conductive path in the resistance variable layer. The second electrode is disposed over the resistance variable layer.
    Type: Application
    Filed: May 16, 2013
    Publication date: September 18, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Chi TU, Chih-Yang CHANG, Hsia-Wei CHEN, Yu-Wen LIAO, Chin-Chieh YANG, Wen-Ting CHU
  • Publication number: 20140259418
    Abstract: In one example, this disclosure describes a method including determining, at a central controller of an air mattress system, whether a user is present on a mattress of the air mattress system, initiating a timer in response to determining that the user is present on the mattress, enabling a light control feature of the air mattress system upon determining that the user is present on the mattress after expiration of the timer, and after enabling the light control feature, transmitting, from the central controller, at least one instruction to turn on at least one light of the air mattress system in response to determining that the user is no longer present on the mattress.
    Type: Application
    Filed: March 13, 2014
    Publication date: September 18, 2014
    Inventors: Rob Nunn, Wade Daniel Palashewski, Yi-ching Chen, Steven Young, Carl Hewitt
  • Publication number: 20140264874
    Abstract: Integrated circuit devices and method of forming them. The devices include a dielectric barrier layer formed over a copper-containing metal interconnect structure. The dielectric barrier layer inhibits electro-migration of Cu. The dielectric barrier layer includes a metal-containing layer that forms an interface with the interconnect structure. Incorporating metal within the interfacial layer improves adhesion of the dielectric barrier layer to copper lines and the like and provides superior electro-migration resistance over the operating lifetime of the devices.
    Type: Application
    Filed: August 15, 2013
    Publication date: September 18, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Su-Jen Sung, Chih-Chiang Chang, Chia-Ho Chen
  • Publication number: 20140268621
    Abstract: An electric apparatus is adapted to be electrically coupled to a target platform. The electric apparatus includes a first printed circuit including a first surface parallel to a first plane and a second surface parallel to a second plane perpendicular to the first plane. The first surface has a first area and the second surface has a second area smaller than the first area. A multitude of conductive traces are formed in a layer of the first printed circuit parallel to the first plane. First and second contact regions respectively overlay first and second portions of the second surface. The first and second contact regions are electrically connected to first and second ones of the multitude of conductive traces respectively. The first printed circuit is coupled to the target platform at the first and second contact regions when the first printed circuit is electrically coupled to the target platform.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: Wintec Industries, Inc.
    Inventor: Kong-Chen Chen
  • Publication number: 20140272680
    Abstract: A method for repairing a phase-defect region in a patterned mask for extreme ultraviolet lithography (EUVL) is disclosed. A patterned mask for EUVL is received. The patterned mask includes an absorptive region having an absorption layer over a defect-repairing-enhancement (DRE) layer, a reflective region having the DRE layer without the absorption layer on top of it, a defect and a phase-defect region resulting from the defect and intruding the reflective region. A location and a shape of the phase-defect region is determined. A portion or portions of the DRE layer in the reflective region is removed according to the location and the shape of the phase-defect region to compensate the effect of the phase-defect region.
    Type: Application
    Filed: July 19, 2013
    Publication date: September 18, 2014
    Applicant: Taiwan Simiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Cheng Lu, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Publication number: 20140270058
    Abstract: A detection device for a CT system comprises a low-energy detector assembly; and a high-energy detector assembly disposed under the low-energy detector assembly. The high-energy detector assembly comprises: a plurality of rows of high-energy detectors arranged at predetermined intervals. With the detection device, detectors and data acquisition units are greatly reduced. A high-resolution three-dimensional CT image is acquired while high-accuracy hazardous article alarm is achieved. The cost of manufacture of the system is greatly decreased while high system performance is ensured.
    Type: Application
    Filed: July 15, 2013
    Publication date: September 18, 2014
    Applicant: Nuctech Company Limited
    Inventors: Li Zhang, Zhiqiang Chen, Yuanjing Li, Mingliang Li
  • Publication number: 20140264885
    Abstract: A plurality of macro and micro alignment marks may be formed on a wafer. The macro alignment marks may be formed in pairs at opposite edges of the wafer. The micro alignment marks may be formed to align to streets on the wafer along a first and second direction. A molding compound may be formed on the wafer. The macro alignment marks may be exposed from the molding compound. A pair of the micro alignment marks may be exposed from the molding compound at opposite ends of the streets along the first and the second direction. The wafer may be aligned to a dicing tool using pairs of the macro alignment marks. The dicing tool may be aligned to the streets using pairs of the micro alignment marks. The wafer may be diced using successive pairs of micro alignment marks along the first and second direction.
    Type: Application
    Filed: April 23, 2013
    Publication date: September 18, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Peng Tsai, Wen-Hsiung Lu, Cheng-Ting Chen, Hsien-Wei Chen, Ming-Da Cheng, Chung-Shi Liu
  • Publication number: 20140264929
    Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers.
    Type: Application
    Filed: July 8, 2013
    Publication date: September 18, 2014
    Inventors: Shu-Ting Tsai, Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Chih-Hui Huang, Sheng-Chau Chen, Shih-Pei Chou, Chia-Chieh Lin
  • Publication number: 20140266343
    Abstract: Techniques for reducing noise and power consumption in a loop filter for a phase-locked loop (PLL) are described herein. In one embodiment, a loop filter for a PLL comprises a first proportional capacitor, a second proportional capacitor, an active device, and a plurality of switches. The plurality of switches are configured to alternately couple the first proportional capacitor and the second proportional capacitor to a first charge pump, to alternately couple noise from the active device to the first proportional capacitor and the second proportional capacitor, and to alternately couple the first proportional capacitor and the second proportional capacitor into a feedback circuit, wherein the feedback circuit produces an output voltage of the loop filter.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Inventors: Yu Song, Nan Chen