Patents by Inventor Chen An

Chen An has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8850366
    Abstract: A method for making a mask for an integrated circuit (IC) design includes receiving an IC design layout having a plurality IC features and performing a targeted-feature-surrounding (TFS) checking operation to identify a targeted-feature-surrounding-location (TFSL) in the IC design layout. The method also includes inserting a phase-bar (PB) to the TFSL, performing an optical proximity correction (OPC) to the IC design layout having the PB to form a modified IC design layout and providing the modified IC design layout for fabrication of the mask.
    Type: Grant
    Filed: August 1, 2012
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ru-Gun Liu, Shuo-Yen Chou, Hoi-Tou Ng, Ken-Hsien Hsieh, Yi-Yin Chen
  • Patent number: 8848817
    Abstract: A method for mapping data in a wireless communication system. The method includes generating a precoding matrix for multi-antenna transmission based on a precoding matrix indicator (PMI) feedback from at least one remote receiver where the PMI indicates a choice of precoding matrix derived from a matrix multiplication of two matrices from a first code book and a second codebook. The method further includes precoding one or more layers of a data stream with the precoding matrix and transmitting the preceded layers of data stream to the remove receiver.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: September 30, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Eko Onggosanusi, Runhua Chen
  • Patent number: 8846438
    Abstract: A solar cell includes an absorber layer formed of a CIGAS, copper, indium, gallium, aluminum, and selenium. A method for forming the absorber layer provides for using an indium-aluminum target and depositing an aluminum-indium film as a metal precursor layer using sputter deposition. Additional metal precursor layers such as a CuGa layer are also provided and a thermal processing operation causes the selenization of the metal precursor layers. The thermal processing operation/selenization operation converts the metal precursor layers to an absorber layer. In some embodiments, the absorber layer includes a double graded chalcopyrite-based bandgap.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: September 30, 2014
    Assignee: TSMC Solar Ltd.
    Inventors: Wen-Tsai Yen, Chung-Hsien Wu, Shih-Wei Chen, Wen-Chin Lee
  • Patent number: 8846958
    Abstract: Processes for preparing and purifying lubiprostone are disclosed. Intermediates and preparation thereof are also disclosed.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: September 30, 2014
    Assignee: Scinopharm (Kunshan) Biochemical Technology Co., Ltd.
    Inventors: Julian Paul Henschke, Yuanlian Liu, Lizhen Xia, Yung-Fa Chen
  • Patent number: 8849015
    Abstract: Described herein is a three-dimensional scanning system that features a camera integrated with a user-guided haptic interface device. The system allows an operator, through the sense of touch, to intuitively and interactively identify optimum locations for obtaining images or scans of an object. The system then assembles these scans to produce a virtual three-dimensional representation of the object with a high degree of accuracy and with a minimum of data artifacts.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: September 30, 2014
    Assignee: 3D Systems, Inc.
    Inventors: Larry Bodony, Dan Cookson, Curt Rawley, David Tzu-Wei Chen
  • Patent number: 8848005
    Abstract: A display device including a timing controller, a data driving circuit and a display system is provided. The timing controller outputs first pixel data according to input pixel data, wherein a color depth of the first pixel data is a first bit number or a second bit number smaller than the first bit number. The data driving circuit receives the first pixel data and a notice signal, and maps the first pixel data to generate second pixel data according to the notice signal when the color depth of the first pixel data is the second bit number, and directly takes the first pixel data as the second pixel data when the color depth of the first pixel data is the first bit number, and generates at least one driving voltage according to the second pixel data, wherein the color depth of the second pixel data is the first bit number.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: September 30, 2014
    Assignee: Novatek Microelectronics Corp.
    Inventor: Min-Jung Chen
  • Patent number: 8850453
    Abstract: Described are techniques for event notification. A first notification about a first event is received. A timer is set to an amount of time. Processing waits until an occurrence of either receiving a second notification of a second event or expiration of said timer indicating that the amount of time has lapsed. It is determined whether the amount of time has lapsed or whether the second notification has been received. If the expiration time has lapsed, notification of the first event is provided, and otherwise, if the second notification has been received prior to the amount of time lapsing, the timer is reset and processing waits for an occurrence of either receiving a next notification of an event or expiration of the timer indicating that the amount of time has lapsed.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: September 30, 2014
    Assignee: EMC Corporation
    Inventors: Hongzhen Zhang, Bruce R. Rabe, Scott E. Joyce, Pauline Chen, Neil F. Schutzman
  • Patent number: 8847332
    Abstract: A high voltage semiconductor device is provided. The device includes a semiconductor substrate having a high voltage well with a first conductivity type therein. A gate structure is disposed on the semiconductor substrate of the high voltage well. A source doped region and a drain doped region are in the high voltage well on both sides of the gate structure, respectively. A lightly doped region with the first conductivity type is between the source and drain doped regions and relatively near to the source doped region. The disclosure also presents a method for fabricating a high voltage semiconductor device.
    Type: Grant
    Filed: April 20, 2011
    Date of Patent: September 30, 2014
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Wei-Chun Chou, Yi-Hung Chiu, Chu-Feng Chen, Cheng-Yi Hsieh, Chung-Ren Lao
  • Patent number: 8848115
    Abstract: The present invention provides a 3D image signal controlling method. The method comprises inputting a left eye image into the first liquid crystal layer, turning off the backlight module and switching gray levels of the second liquid crystal layer to a minimum gray level during (4N?3)th time interval, wherein N is natural number; stopping inputting the left eye image, turning on the backlight module and remaining the gray levels of the second liquid crystal layer as the minimum gray level during (4N?2)th time interval; inputting a right eye image into the first liquid crystal layer, turning off the backlight module and switching the gray levels of the second liquid crystal layer as a maximum gray level during (4N?1)th time interval; and stopping inputting the right eye image, turning on the backlight module and remaining the gray levels of the second liquid crystal layer as the maximum gray level during (4N)th time interval.
    Type: Grant
    Filed: November 27, 2010
    Date of Patent: September 30, 2014
    Assignee: Chunghwa Picture Tubes, Ltd.
    Inventors: Shih-Chieh Lin, Hsiang-Tan Lin, Chien-Hung Chen, Chun-Chieh Chiu
  • Patent number: 8846758
    Abstract: Methods for treating abnormal glycosylated hemoglobin (HbA1c) levels in a patient in need thereof, wherein the provided methods comprise administering to a patient in need a therapeutically effective amount of an Interleukin-1? modulator. Also, the invention provides compositions comprising at least one lipid modifying agent and an IL-1? modulator.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: September 30, 2014
    Assignee: TWi Biotechnology, Inc.
    Inventors: Mannching Sherry Ku, Chih-Kuang Chen, Wei-Shu Lu, Chih-Ming Chen, I-Yin Lin
  • Patent number: 8850370
    Abstract: A layout method of a semiconductor circuit is provided. The layout method is firstly putting a plurality of circuit patterns on a substrate, wherein a first distance is the largest distance between any one of the circuit patterns and one of other circuit patterns adjacent thereto. The layout method is then determining whether the first distance is larger than a first critical value. Later, when the first distance is larger than the first critical value, at least a closed loop dummy pattern is putted in one of the areas corresponding to the first distance between the pair of the circuit patterns. The closed loop dummy pattern is putted in a same layer with the circuit patterns, surrounds between the pair of circuit patterns and is insulated from the circuit patterns.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: September 30, 2014
    Assignee: United Microelectronics Corporation
    Inventors: Chia-Chen Sun, Shih-Chieh Hsu, Yi-Chung Sheng, Sheng-Yuan Hsueh, Yao-Chang Wang
  • Patent number: 8850368
    Abstract: One or more techniques or systems for determining double patterning technology (DPT) layout routing compliance are provided herein. For example, a layout routing component of a system is configured to assign a pin loop value to a pin loop. In some embodiments, the pin loop value is assigned based on a mask assignment of a pin of the pin loop. In some embodiments, the pin loop value is assigned based on a number of nodes associated with the pin loop. DPT compliance or a DPT violation is determined for the pin loop based on the pin loop value. In this manner, odd loop detection associated with DPT layout routing is provided because a DPT violation results in generation of an additional instance of a net, for example. Detecting an odd loop allows a design to be redesigned before fabrication, where the odd loop would present undesired issues.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Huang-Yu Chen, Fang-Yu Fan, Yuan-Te Hou, Wen-Hao Chen, Chung-Hsing Wang, Yi-Kan Cheng
  • Patent number: 8846295
    Abstract: The present invention relates to a photoresist composition capable of negative development and a pattern forming method using the photoresist composition. The photoresist composition includes an imaging polymer, a crosslinking agent and a radiation sensitive acid generator. The imaging polymer includes a monomeric unit having an acid-labile moiety-substituted hydroxyl group. The patterning forming method utilizes an organic solvent developer to selectively remove an unexposed region of a photoresist layer of the photoresist composition to form a patterned structure in the photoresist layer. The photoresist composition and the pattern forming method are especially useful for forming material patterns on a semiconductor substrate using 193 nm (ArF) lithography.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: September 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kuang-Jung Chen, Wu-Song Huang, Wai-Kin Li
  • Patent number: 8847397
    Abstract: Provided are MIM DRAM capacitors and methods of forming thereof. A MIM DRAM capacitor may include an electrode layer formed from a high work function material (e.g., greater than about 5.0 eV). This layer may be used to reduce the leakage current through the capacitor. The capacitor may also include another electrode layer having a high conductivity base portion and a conductive metal oxide portion. The conductive metal oxide portion serves to promote the growth of the high k phase of the dielectric layer.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: September 30, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Sandra G. Malhotra, Hanhong Chen, Wim Deweerd, Arthur Gevondyan, Hiroyuki Ode
  • Patent number: 8850369
    Abstract: A method for optimizing masks used for forming conductive features and a method for creating the mask features on an IC device are disclosed. An exemplary embodiment includes receiving a design database including a plurality of conductive features. First and second features suitable for joining are identified from the plurality of conductive features. A joined feature corresponding to the first and the second features is characterized. A cut shape configured to separate the first and second features from the joined feature is also characterized. The joined feature is categorized into a first conductive mask, the cut shape is categorized into a cut mask, and a third feature is categorized into a second conductive mask. The categorized shapes and features of the first conductive mask, the second conductive mask, and the cut mask are provided for manufacturing a mask set corresponding to the categorized shapes and features.
    Type: Grant
    Filed: April 20, 2012
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yuan-Hsiang Lung, Kuei-Shun Chen, Meng-Wei Chen, Chia-Ying Lee
  • Patent number: 8846894
    Abstract: The present invention concerns methods and reagents useful in modulating gene expression in a variety of applications, including use in therapeutic, diagnostic, target validation, and genomic discovery applications. Specifically, the invention relates to synthetic chemically modified small nucleic acid molecules, such as short interfering nucleic acid (siNA), short interfering RNA (siRNA), double-stranded RNA (dsRNA), micro-RNA (miRNA), and short hairpin RNA (shRNA) molecules capable of mediating RNA interference (RNAi) against target nucleic acid sequences. The small nucleic acid molecules are useful in the treatment of any disease or condition that responds to modulation of gene expression or activity in a cell, tissue, or organism.
    Type: Grant
    Filed: February 16, 2007
    Date of Patent: September 30, 2014
    Assignee: Sirna Therapeutics, Inc.
    Inventors: James McSwiggen, Bharat Chowrira, Leonid Beigelman, Dennis Macejak, Shawn Zinnen, Pamela Pavco, Peter Haeberli, David Morrissey, Kathy Fosnaugh, Sharon F Jamison, Nassim Usman, James Thompson, Chandra Vargeese, Weimin Wang, Tongqian Chen, Narendra K Vaish
  • Patent number: 8846323
    Abstract: Embodiments of the present disclosure provide for enzyme sensors, protease sensors, methods for producing and using the enzyme and protease sensors, methods of detecting and/or measuring protease activity, methods for characterizing protease cellular activity, fusion proteins, polynucleotides, and vectors corresponding to the enzyme and protease sensors, kits, and the like.
    Type: Grant
    Filed: March 21, 2013
    Date of Patent: September 30, 2014
    Assignee: Georgia State University Research Foundation, Inc.
    Inventors: Jenny J. Yang, Ning Chen
  • Patent number: 8846768
    Abstract: Novel Uses of small molecules, particularly, triterpenoids and ingol diterpenes isolated from Euphorbia neriifolia, are disclosed herein. The triterpenoids are useful as lead compounds for manufacturing a medicament or a pharmaceutical composition for treating cancer; whereas the ingol diterpenes are useful as lead compounds for manufacturing a medicament or a pharmaceutical composition for treating thrombocytopenia.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: September 30, 2014
    Assignee: Mackay Memorial Hospital
    Inventors: Yu-Jen Chen, Lie-Chwn Lin, Ching-Pin Lin
  • Patent number: 8848412
    Abstract: A ternary content addressable memory (TCAM) has at least one TCAM cell comprising first and second memory bitcells for storing first and second bit values representing a cell state comprising one of a first cell state, a second cell state and a mask cell state. The first and second memory bitcells share a pair of bitlines for accessing the first and second bit values. Access control circuitry is provided for triggering, in response to a clock signal, a read or write access to the first memory bitcell during a first portion of a clock cycle and triggering a read access or write access to the second read bitcell during a second portion of the clock cycle.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: September 30, 2014
    Assignee: ARM Limited
    Inventors: Gus Yeung, Yew Keong Chong, Wang-Kun Chen
  • Patent number: D714488
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: September 30, 2014
    Assignees: Shanghai Sansi Electronics Engineering Co., Ltd., Shanghai Sansi Technology Co., Ltd, Jiashan Sansi Photoelectricity Technology Co., Ltd.
    Inventors: Bishou Chen, Huer Chu, Na Feng, Wanmei Cheng