Patents by Inventor Chen-Cheng Chou

Chen-Cheng Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11221550
    Abstract: A projection device includes a laser light source and a wavelength conversion assembly. The laser light source is configured to emit a first laser light having a first wavelength. The wavelength conversion assembly is configured to convert a first portion of the first laser light into a second laser light, wherein the second laser light has a second wavelength different from the first wavelength. The second laser light is reflected back to an upstream optical path of the wavelength conversion assembly through the wavelength conversion assembly, and a second portion of the first laser light is reflected to a downstream optical path of the wavelength conversion assembly through the wavelength conversion assembly.
    Type: Grant
    Filed: January 22, 2021
    Date of Patent: January 11, 2022
    Assignees: BENQ CORPORATION, BenQ Intelligent Technology (Shanghai) Co., Ltd
    Inventors: Chen-Cheng Huang, Tung-Chia Chou
  • Patent number: 11106120
    Abstract: A projection device, a light source system and a projection method thereof are provided. A portion of the light-emitting units are controlled to provide a light beam as the first light beam. It is detected whether characteristic parameters of the light-emitting units providing the light beam reach a preset value. When the preset value is not reached, the light-emitting units providing the light beam are disabled, and the remaining light-emitting units are controlled to provide the back-up light beam as the first light beam. A portion of the first light beam is converted into a second light beam. The first light beam of which the wavelength is not converted and the second light beam are combined to generate an illumination beam. The illumination beam is converted into an image beam. The image beam is converted into a projection beam.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: August 31, 2021
    Assignee: Coretronic Corporation
    Inventors: Chen-Cheng Chou, Jeng-An Liao, Fu-Shun Kao, Hung-Lin Chen, Hsin-Chang Huang
  • Publication number: 20210043518
    Abstract: A method for manufacturing a semiconductor structure includes etching trenches in a semiconductor substrate to form a semiconductor fin between the trenches; converting sidewalls of the semiconductor fin into hydrogen-terminated surfaces each having silicon-to-hydrogen (S—H) bonds; after converting the sidewalls of the semiconductor fin into the hydrogen-terminated surfaces, depositing a dielectric material overfilling the trenches; and etching back the dielectric material to fall below a top surface of the semiconductor fin.
    Type: Application
    Filed: October 23, 2020
    Publication date: February 11, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Cheng CHOU, Shiu-Ko JANGJIAN, Cheng-Ta WU
  • Patent number: 10818558
    Abstract: A method for manufacturing a semiconductor structure is provided. A plurality of trenches are formed in a substrate. The trenches define at least one fin therebetween. The fin is hydrogen annealed. A dielectric material is formed in the trenches. The dielectric material in the trenches is recessed.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: October 27, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Cheng Chou, Shiu-Ko Jangjian, Cheng-Ta Wu
  • Publication number: 20200081332
    Abstract: An illumination system, a projection apparatus and an illumination control method are provided. The illumination system includes an excitation light source, an optical component, a light source driver, a temperature sensing module and a controller. The excitation light source emits an excitation light beam. The optical component is located on a transmission path of the excitation light beam. The light source driver is configured to drive the excitation light source. The temperature sensing module is located in a neighboring region of the optical component and configured to sense a temperature of the neighboring region of the optical component to output a sensing voltage. The controller is configured to receive the sensing voltage to determine whether the sensing voltage falls out of a predetermined voltage range and configured to output a control signal to the light source driver to adjust the excitation light beam.
    Type: Application
    Filed: September 5, 2019
    Publication date: March 12, 2020
    Applicant: Coretronic Corporation
    Inventors: Chen-Cheng Chou, Jeng-An Liao, Chun-Hsien Wu, Fu-Shun Kao, Hung-Lin Chen, Hsin-Chang Huang
  • Publication number: 20200073221
    Abstract: A projection device, a light source system and a projection method thereof are provided. A portion of the light-emitting units are controlled to provide a light beam as the first light beam. It is detected whether characteristic parameters of the light-emitting units providing the light beam reach a preset value. When the preset value is not reached, the light-emitting units providing the light beam are disabled, and the remaining light-emitting units are controlled to provide the back-up light beam as the first light beam. A portion of the first light beam is converted into a second light beam. The first light beam of which the wavelength is not converted and the second light beam are combined to generate an illumination beam. The illumination beam is converted into an image beam. The image beam is converted into a projection beam.
    Type: Application
    Filed: August 29, 2019
    Publication date: March 5, 2020
    Applicant: Coretronic Corporation
    Inventors: Chen-Cheng Chou, Jeng-An Liao, Fu-Shun Kao, Hung-Lin Chen, Hsin-Chang Huang
  • Publication number: 20190384147
    Abstract: A light detecting element for detecting rotations of a wheel is provided. The light detecting element includes a circuit board and an optical transceiver component. The circuit board has a first conductive layer and a first insulation layer. The first conductive layer has a first heat dissipation region, and the first insulation layer covers the first conductive layer and exposes the first heat dissipation region. The optical transceiver component is disposed on the first heat dissipation region and electrically connected to the circuit board. The optical transceiver component includes a light emitter and a light receiver, the light emitter is adapted to emit a light signal to the wheel, and the light receiver is adapted to receive the light signal reflected from the wheel. The invention further provides a projection apparatus having the light detecting element.
    Type: Application
    Filed: April 12, 2019
    Publication date: December 19, 2019
    Inventors: WEN-HAO CHU, YIN-NAN LAI, JENG-AN LIAO, CHEN-CHENG CHOU, TUNG-CHOU HU
  • Patent number: 9570557
    Abstract: Techniques in fabricating a fin field-effect transistor (FinFET) include providing a substrate having a fin structure and forming an isolation region having a top surface with a first surface profile. A dopant species is implanted using a tilt angle to edge portions of the top surface. The edge portions are then removed using an etch process. In this respect, the isolation region is modified to have a second surface profile based on an etching rate that is greater than an etching rate used at other portions of the top surface. The second surface profile has a step height that is smaller than a step height corresponding to the first surface profile. The tilt implantation and etching process can be performed before a gate structure is formed, after the gate structure is formed but before the fin structure is recessed, or after the fin structure is recessed.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: February 14, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen Cheng Chou, Chung-Ren Sun, Chii-Ming Wu, Cheng-Ta Wu, Tzu kai Lin
  • Publication number: 20160322462
    Abstract: Techniques in fabricating a fin field-effect transistor (FinFET) include providing a substrate having a fin structure and forming an isolation region having a top surface with a first surface profile. A dopant species is implanted using a tilt angle to edge portions of the top surface. The edge portions are then removed using an etch process. In this respect, the isolation region is modified to have a second surface profile based on an etching rate that is greater than an etching rate used at other portions of the top surface. The second surface profile has a step height that is smaller than a step height corresponding to the first surface profile. The tilt implantation and etching process can be performed before a gate structure is formed, after the gate structure is formed but before the fin structure is recessed, or after the fin structure is recessed.
    Type: Application
    Filed: April 29, 2015
    Publication date: November 3, 2016
    Inventors: Chen Cheng CHOU, Chung-Ren SUN, Chii-Ming WU, Cheng-Ta WU, Tzu kai LIN
  • Publication number: 20160315014
    Abstract: A method for manufacturing a semiconductor structure is provided. A plurality of trenches are formed in a substrate. The trenches define at least one fin therebetween. The fin is hydrogen annealed. A dielectric material is formed in the trenches. The dielectric material in the trenches is recessed.
    Type: Application
    Filed: June 12, 2015
    Publication date: October 27, 2016
    Inventors: Chen-Cheng CHOU, Shiu-Ko JANGJIAN, Cheng-Ta WU
  • Patent number: 8779572
    Abstract: A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: July 15, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuan-Yi Lin, Ching-Chen Hao, Chen Cheng Chou, Sheng-Yuan Lin
  • Patent number: 8742583
    Abstract: The formation of a seal ring in a semiconductor integrated circuit (IC) die is described. Through-silicon vias (TSVs) are typically formed in a semiconductor IC die to facilitate the formation of a three dimensional (3D) stacking die structure. The TSVs may be utilized to provide electrical connections between components in different dies of the 3D stacking die structure. A seal ring is formed in the inter-metal dielectric (IMD) layers of an IC die, enclosing an active circuit region. The real ring is formed prior to the formation of the TSVs, preventing moistures or other undesired chemical agents from diffusing into the active circuit region during the subsequent processes of forming TSVs.
    Type: Grant
    Filed: January 16, 2012
    Date of Patent: June 3, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuan-Yi Lin, Ching-Chen Hao, Chen Cheng Chou, Sheng-Yuan Lin
  • Publication number: 20140054761
    Abstract: A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.
    Type: Application
    Filed: November 5, 2013
    Publication date: February 27, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuan-Yi Lin, Ching-Chen Hao, Chen Cheng Chou, Sheng-Yuan Lin
  • Patent number: 8609506
    Abstract: A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: December 17, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuan-Yi Lin, Ching-Chen Hao, Chen Cheng Chou, Sheng-Yuan Lin
  • Publication number: 20130002654
    Abstract: A three-dimensional (3D) glasses and a method for operating the same are provided. The 3D glasses includes a first lens, a second lens, an infrared receiver and a control unit. The infrared receiver receives an infrared signal to output a digital control signal. The control unit is coupled to the infrared receiver. The control unit controls a first state of the first lens and a second state of the second lens according to a first pulse of the digital control signal, where at least one of the first state and the second state is an OFF state.
    Type: Application
    Filed: April 1, 2012
    Publication date: January 3, 2013
    Applicant: CORETRONIC CORPORATION
    Inventors: Tse-Fan Yeh, Chen-Cheng Chou, Chun-Chieh Chen, Shu-Hui Liao, Jeng-An Liao, Chun-Hao Chen
  • Patent number: 8314483
    Abstract: A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: November 20, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuan-Yi Lin, Ching-Chen Hao, Chen Cheng Chou, Sheng-Yuan Lin
  • Patent number: 8207567
    Abstract: A stacked metal-oxide-metal (MOM) capacitor structure and method of forming the same to increase an electrode/capacitor dielectric coupling area to increase a capacitance, the MOM capacitor structure including a plurality of metallization layers in stacked relationship; wherein each metallization layer includes substantially parallel spaced apart conductive electrode line portions having a first intervening capacitor dielectric; and, wherein the conductive electrode line portions are electrically interconnected between metallization layers by conductive damascene line portions formed in a second capacitor dielectric and disposed underlying the conductive electrode line portions.
    Type: Grant
    Filed: November 19, 2008
    Date of Patent: June 26, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao-Chi Chin, Ming-Chu King, Chen Cheng Chou
  • Publication number: 20120112322
    Abstract: The formation of a seal ring in a semiconductor integrated circuit (IC) die is described. Through-silicon vias (TSVs) are typically formed in a semiconductor IC die to facilitate the formation of a three dimensional (3D) stacking die structure. The TSVs may be utilized to provide electrical connections between components in different dies of the 3D stacking die structure. A seal ring is formed in the inter-metal dielectric (IMD) layers of an IC die, enclosing an active circuit region. The real ring is formed prior to the formation of the TSVs, preventing moistures or other undesired chemical agents from diffusing into the active circuit region during the subsequent processes of forming TSVs.
    Type: Application
    Filed: January 16, 2012
    Publication date: May 10, 2012
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chuan-Yi Lin, Ching-Chen Hao, Chen Cheng Chou, Sheng-Yuan Lin
  • Patent number: 8168529
    Abstract: The formation of a seal ring in a semiconductor integrated circuit (IC) die is described. Through-silicon vias (TSVs) are typically formed in a semiconductor IC die to facilitate the formation of a three dimensional (3D) stacking die structure. The TSVs may be utilized to provide electrical connections between components in different dies of the 3D stacking die structure. A seal ring is formed in the inter-metal dielectric (IMD) layers of an IC die, enclosing an active circuit region. The real ring is formed prior to the formation of the TSVs, preventing moistures or other undesired chemical agents from diffusing into the active circuit region during the subsequent processes of forming TSVs.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: May 1, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuan-Yi Lin, Ching-Chen Hao, Chen Cheng Chou, Sheng-Yuan Lin
  • Publication number: 20100187671
    Abstract: The formation of a seal ring in a semiconductor integrated circuit (IC) die is described. Through-silicon vias (TSVs) are typically formed in a semiconductor IC die to facilitate the formation of a three dimensional (3D) stacking die structure. The TSVs may be utilized to provide electrical connections between components in different dies of the 3D stacking die structure. A seal ring is formed in the inter-metal dielectric (IMD) layers of an IC die, enclosing an active circuit region. The real ring is formed prior to the formation of the TSVs, preventing moistures or other undesired chemical agents from diffusing into the active circuit region during the subsequent processes of forming TSVs.
    Type: Application
    Filed: November 13, 2009
    Publication date: July 29, 2010
    Inventors: Chuan-Yi Lin, Ching-Chen Hao, Chen Cheng Chou, Sheng-Yuan Lin