Patents by Inventor Chen-Cheng Chou

Chen-Cheng Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240412670
    Abstract: A projection device and a driving method of the projection device are provided. The projection device includes a signal processing circuit, a driving circuit, a light-emitting module, and a discharge circuit. The signal processing circuit is configured to provide a modulation signal and a first signal. The driving circuit is coupled to the signal processing circuit and a driving node. The driving circuit is configured to generate a driving signal to the driving node according to the modulation signal. The light-emitting module is coupled to the driving circuit through the driving node. The light-emitting module is configured to receive the driving signal from the driving node to accordingly emit a laser beam. The discharge circuit is coupled to the signal processing circuit and the driving node. The discharge circuit is configured to provide a reference voltage to the driving node according to the first signal.
    Type: Application
    Filed: June 3, 2024
    Publication date: December 12, 2024
    Applicant: Coretronic Corporation
    Inventors: You-Xuan Kuo, Chen-Cheng Chou, Jeng-An Liao
  • Publication number: 20240411334
    Abstract: A circuit includes a memory macro comprising a plurality of memory banks. The circuit includes a first voltage regulator configured to provide a first operation voltage to the memory macro at a first output node. The circuit includes a second voltage regulator configured to provide a second operation voltage to the memory macro at a second output node. The second operation voltage is substantially higher than the first operation voltage. The circuit includes a decoupling capacitor configured to be alternately shared by the first voltage regulator when the memory macro receives the first operation voltage, and by the second voltage regulator when the memory macro receives the second operation voltage.
    Type: Application
    Filed: June 8, 2023
    Publication date: December 12, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zheng-Jun Lin, Chen-Ming Hung, Chung-Cheng Chou
  • Publication number: 20240395566
    Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Inventors: Zi-Jheng Liu, Yu-Hsiang Hu, Jo-Lin Lan, Sih-Hao Liao, Chen-Cheng Kuo, Hung-Jui Kuo, Chung-Shi Liu, Chen-Hua Yu, Meng-Wei Chou
  • Publication number: 20240363461
    Abstract: A device including a substrate, a front-end module circuit situated over the substrate and configured to provide radio frequency communications, and a wafer-level chip-scale package circuit situated over the front-end module circuit and connected to the front-end module circuit and configured to provide passive components for radio frequency communications.
    Type: Application
    Filed: April 28, 2023
    Publication date: October 31, 2024
    Inventors: Hsieh-Hung Hsieh, Chen Cheng Chou, Hwa-Yu Yang, Ming-Da Cheng, Ru-Shang Hsiao, Tzu-Jin Yeh, Ching-Hui Chen, Shenggao Li
  • Patent number: 12133474
    Abstract: A method of fabricating magnetoresistive random access memory, including providing a substrate, forming a bottom electrode layer, a magnetic tunnel junction stack, a top electrode layer and a hard mask layer sequentially on the substrate, wherein a material of the top electrode layer is titanium nitride, a material of the hard mask layer is tantalum or tantalum nitride, and a percentage of nitrogen in the titanium nitride gradually decreases from a top surface of top electrode layer to a bottom surface of top electrode layer, and patterning the bottom electrode layer, the magnetic tunnel junction stack, the top electrode layer and the hard mask layer into multiple magnetoresistive random access memory cells.
    Type: Grant
    Filed: September 27, 2023
    Date of Patent: October 29, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, Jing-Yin Jhang, I-Ming Tseng, Yu-Ping Wang, Chien-Ting Lin, Kun-Chen Ho, Yi-Syun Chou, Chang-Min Li, Yi-Wei Tseng, Yu-Tsung Lai, Jun Xie
  • Patent number: 12119267
    Abstract: A method includes forming patterned masks over a semiconductor substrate; etching the semiconductor substrate using the patterned masks as an etch mask to form semiconductor fins with a trench between the semiconductor fins; performing an annealing process using a hydrogen containing gas to smooth surfaces of the semiconductor fins; after performing the annealing process, selectively forming a first liner on the smoothed surfaces of the semiconductor fins, while leaving surfaces of the patterned masks exposed by the first liner; filling the trench with a dielectric material; and etching back the first liner and the dielectric material to form an isolation structure between the semiconductor fins.
    Type: Grant
    Filed: January 6, 2023
    Date of Patent: October 15, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Cheng Chou, Shiu-Ko Jangjian, Cheng-Ta Wu
  • Patent number: 12094728
    Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.
    Type: Grant
    Filed: May 26, 2023
    Date of Patent: September 17, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Zi-Jheng Liu, Yu-Hsiang Hu, Jo-Lin Lan, Sih-Hao Liao, Chen-Cheng Kuo, Hung-Jui Kuo, Chung-Shi Liu, Chen-Hua Yu, Meng-Wei Chou
  • Publication number: 20230154799
    Abstract: A method includes forming patterned masks over a semiconductor substrate; etching the semiconductor substrate using the patterned masks as an etch mask to form semiconductor fins with a trench between the semiconductor fins; performing an annealing process using a hydrogen containing gas to smooth surfaces of the semiconductor fins; after performing the annealing process, selectively forming a first liner on the smoothed surfaces of the semiconductor fins, while leaving surfaces of the patterned masks exposed by the first liner; filling the trench with a dielectric material; and etching back the first liner and the dielectric material to form an isolation structure between the semiconductor fins.
    Type: Application
    Filed: January 6, 2023
    Publication date: May 18, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Cheng CHOU, Shiu-Ko JANGJIAN, Cheng-Ta WU
  • Patent number: 11551979
    Abstract: A method for manufacturing a semiconductor structure includes etching trenches in a semiconductor substrate to form a semiconductor fin between the trenches; converting sidewalls of the semiconductor fin into hydrogen-terminated surfaces each having silicon-to-hydrogen (S—H) bonds; after converting the sidewalls of the semiconductor fin into the hydrogen-terminated surfaces, depositing a dielectric material overfilling the trenches; and etching back the dielectric material to fall below a top surface of the semiconductor fin.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: January 10, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Cheng Chou, Shiu-Ko Jangjian, Cheng-Ta Wu
  • Patent number: 11106120
    Abstract: A projection device, a light source system and a projection method thereof are provided. A portion of the light-emitting units are controlled to provide a light beam as the first light beam. It is detected whether characteristic parameters of the light-emitting units providing the light beam reach a preset value. When the preset value is not reached, the light-emitting units providing the light beam are disabled, and the remaining light-emitting units are controlled to provide the back-up light beam as the first light beam. A portion of the first light beam is converted into a second light beam. The first light beam of which the wavelength is not converted and the second light beam are combined to generate an illumination beam. The illumination beam is converted into an image beam. The image beam is converted into a projection beam.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: August 31, 2021
    Assignee: Coretronic Corporation
    Inventors: Chen-Cheng Chou, Jeng-An Liao, Fu-Shun Kao, Hung-Lin Chen, Hsin-Chang Huang
  • Publication number: 20210043518
    Abstract: A method for manufacturing a semiconductor structure includes etching trenches in a semiconductor substrate to form a semiconductor fin between the trenches; converting sidewalls of the semiconductor fin into hydrogen-terminated surfaces each having silicon-to-hydrogen (S—H) bonds; after converting the sidewalls of the semiconductor fin into the hydrogen-terminated surfaces, depositing a dielectric material overfilling the trenches; and etching back the dielectric material to fall below a top surface of the semiconductor fin.
    Type: Application
    Filed: October 23, 2020
    Publication date: February 11, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Cheng CHOU, Shiu-Ko JANGJIAN, Cheng-Ta WU
  • Patent number: 10818558
    Abstract: A method for manufacturing a semiconductor structure is provided. A plurality of trenches are formed in a substrate. The trenches define at least one fin therebetween. The fin is hydrogen annealed. A dielectric material is formed in the trenches. The dielectric material in the trenches is recessed.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: October 27, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Cheng Chou, Shiu-Ko Jangjian, Cheng-Ta Wu
  • Publication number: 20200081332
    Abstract: An illumination system, a projection apparatus and an illumination control method are provided. The illumination system includes an excitation light source, an optical component, a light source driver, a temperature sensing module and a controller. The excitation light source emits an excitation light beam. The optical component is located on a transmission path of the excitation light beam. The light source driver is configured to drive the excitation light source. The temperature sensing module is located in a neighboring region of the optical component and configured to sense a temperature of the neighboring region of the optical component to output a sensing voltage. The controller is configured to receive the sensing voltage to determine whether the sensing voltage falls out of a predetermined voltage range and configured to output a control signal to the light source driver to adjust the excitation light beam.
    Type: Application
    Filed: September 5, 2019
    Publication date: March 12, 2020
    Applicant: Coretronic Corporation
    Inventors: Chen-Cheng Chou, Jeng-An Liao, Chun-Hsien Wu, Fu-Shun Kao, Hung-Lin Chen, Hsin-Chang Huang
  • Publication number: 20200073221
    Abstract: A projection device, a light source system and a projection method thereof are provided. A portion of the light-emitting units are controlled to provide a light beam as the first light beam. It is detected whether characteristic parameters of the light-emitting units providing the light beam reach a preset value. When the preset value is not reached, the light-emitting units providing the light beam are disabled, and the remaining light-emitting units are controlled to provide the back-up light beam as the first light beam. A portion of the first light beam is converted into a second light beam. The first light beam of which the wavelength is not converted and the second light beam are combined to generate an illumination beam. The illumination beam is converted into an image beam. The image beam is converted into a projection beam.
    Type: Application
    Filed: August 29, 2019
    Publication date: March 5, 2020
    Applicant: Coretronic Corporation
    Inventors: Chen-Cheng Chou, Jeng-An Liao, Fu-Shun Kao, Hung-Lin Chen, Hsin-Chang Huang
  • Publication number: 20190384147
    Abstract: A light detecting element for detecting rotations of a wheel is provided. The light detecting element includes a circuit board and an optical transceiver component. The circuit board has a first conductive layer and a first insulation layer. The first conductive layer has a first heat dissipation region, and the first insulation layer covers the first conductive layer and exposes the first heat dissipation region. The optical transceiver component is disposed on the first heat dissipation region and electrically connected to the circuit board. The optical transceiver component includes a light emitter and a light receiver, the light emitter is adapted to emit a light signal to the wheel, and the light receiver is adapted to receive the light signal reflected from the wheel. The invention further provides a projection apparatus having the light detecting element.
    Type: Application
    Filed: April 12, 2019
    Publication date: December 19, 2019
    Inventors: WEN-HAO CHU, YIN-NAN LAI, JENG-AN LIAO, CHEN-CHENG CHOU, TUNG-CHOU HU
  • Patent number: 9570557
    Abstract: Techniques in fabricating a fin field-effect transistor (FinFET) include providing a substrate having a fin structure and forming an isolation region having a top surface with a first surface profile. A dopant species is implanted using a tilt angle to edge portions of the top surface. The edge portions are then removed using an etch process. In this respect, the isolation region is modified to have a second surface profile based on an etching rate that is greater than an etching rate used at other portions of the top surface. The second surface profile has a step height that is smaller than a step height corresponding to the first surface profile. The tilt implantation and etching process can be performed before a gate structure is formed, after the gate structure is formed but before the fin structure is recessed, or after the fin structure is recessed.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: February 14, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen Cheng Chou, Chung-Ren Sun, Chii-Ming Wu, Cheng-Ta Wu, Tzu kai Lin
  • Publication number: 20160322462
    Abstract: Techniques in fabricating a fin field-effect transistor (FinFET) include providing a substrate having a fin structure and forming an isolation region having a top surface with a first surface profile. A dopant species is implanted using a tilt angle to edge portions of the top surface. The edge portions are then removed using an etch process. In this respect, the isolation region is modified to have a second surface profile based on an etching rate that is greater than an etching rate used at other portions of the top surface. The second surface profile has a step height that is smaller than a step height corresponding to the first surface profile. The tilt implantation and etching process can be performed before a gate structure is formed, after the gate structure is formed but before the fin structure is recessed, or after the fin structure is recessed.
    Type: Application
    Filed: April 29, 2015
    Publication date: November 3, 2016
    Inventors: Chen Cheng CHOU, Chung-Ren SUN, Chii-Ming WU, Cheng-Ta WU, Tzu kai LIN
  • Publication number: 20160315014
    Abstract: A method for manufacturing a semiconductor structure is provided. A plurality of trenches are formed in a substrate. The trenches define at least one fin therebetween. The fin is hydrogen annealed. A dielectric material is formed in the trenches. The dielectric material in the trenches is recessed.
    Type: Application
    Filed: June 12, 2015
    Publication date: October 27, 2016
    Inventors: Chen-Cheng CHOU, Shiu-Ko JANGJIAN, Cheng-Ta WU
  • Patent number: 8779572
    Abstract: A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: July 15, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuan-Yi Lin, Ching-Chen Hao, Chen Cheng Chou, Sheng-Yuan Lin
  • Patent number: 8742583
    Abstract: The formation of a seal ring in a semiconductor integrated circuit (IC) die is described. Through-silicon vias (TSVs) are typically formed in a semiconductor IC die to facilitate the formation of a three dimensional (3D) stacking die structure. The TSVs may be utilized to provide electrical connections between components in different dies of the 3D stacking die structure. A seal ring is formed in the inter-metal dielectric (IMD) layers of an IC die, enclosing an active circuit region. The real ring is formed prior to the formation of the TSVs, preventing moistures or other undesired chemical agents from diffusing into the active circuit region during the subsequent processes of forming TSVs.
    Type: Grant
    Filed: January 16, 2012
    Date of Patent: June 3, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuan-Yi Lin, Ching-Chen Hao, Chen Cheng Chou, Sheng-Yuan Lin