Abstract: A high aspect ratio contact structure formed within a dielectric material includes a top portion and a bottom portion. The top portion of the contact structure includes a tapering profile towards the bottom portion. A first metal stack surrounded by an inner spacer is located within the top portion of the contact structure and a second metal stack is located within the bottom portion of the contact structure. A width of the bottom portion of the contact structure is greater than a minimum width of the top portion of the contact structure.

Abstract: An operation method for a memory device is provided. A memory block of the memory device includes an array of memory cells including cell strings and cell pages. Serially numbered and arranged bit lines are connected to the cell strings, respectively. Serially numbered and arranged word lines are connected to the cell pages, respectively. The operation method includes: performing a batch writing to each of the cell pages, such that the memory cells in each cell page are respectively grouped as an earlier written memory cell or a later written memory cell, depending on the connected bit line is either even-numbered or odd-numbered. Each cell page has a respective write sequence. In terms of write sequence, each cell page is identical with one of 2 nearest cell pages, and opposite to the other of the 2 nearest cell pages.

Abstract: Embodiments disclosed herein describe methods of forming semiconductor devices. The methods may include etching vias and trenches in a middle-of-line (MOL) layer that has a low-k dielectric layer, a sacrificial nitride layer, and a hard mask layer. The methods may also include depositing a thin nitride layer within the via trench, depositing a carbon layer on the thin nitride layer within the vias and trenches, etching back the thin nitride layer to expose a portion of the hard mask layer, removing the hard mask layer and the carbon layer, and removing the thin nitride layer and the sacrificial nitride layer.

Abstract: A method of forming stacked vertical field effect devices is provided. The method includes forming a layer stack on a substrate, wherein the layer stack includes a first spacer layer on the substrate, a first protective liner on the first spacer layer, a first gap layer on the first protective liner, a second protective liner on the first gap layer, a second spacer layer on the second protective liner, a sacrificial layer on the second spacer layer, a third spacer layer on the sacrificial layer, a third protective liner on the third spacer layer, a second gap layer on the third protective liner, a fourth protective liner on the second gap layer, and a fourth spacer layer on the fourth protective liner. The method further includes forming channels through the layer stack, a liner layer on the sidewalls of the channels, and a vertical pillar in the channels.

Abstract: The present application provides a digital twin utility tunnel system based on a reduced-order simulation model and a real-time calibration algorithm. The system includes a big data aggregation unit and a real-time simulation deduction unit. The big data aggregation unit is configured to collect static attribute data and real-time dynamic data. The real-time dynamic data includes fixed monitoring data and mobile monitoring data. The fixed monitoring data is collected by gas sensors fixedly installed in the utility tunnel, and the mobile monitoring data is collected by mobile sensors in the utility tunnel. The real-time simulation deduction unit includes a forward prediction module and an inversion calibration module.

Abstract: The present application provides a digital twin utility tunnel system based on a reduced-order simulation model and a real-time calibration algorithm. The system includes a big data aggregation unit and a real-time simulation deduction unit. The big data aggregation unit is configured to collect static attribute data and real-time dynamic data. The real-time dynamic data includes fixed monitoring data and mobile monitoring data. The fixed monitoring data is collected by gas sensors fixedly installed in the utility tunnel, and the mobile monitoring data is collected by mobile sensors in the utility tunnel. The real-time simulation deduction unit includes a forward prediction module and an inversion calibration module.

Abstract: Techniques for area scaling of contacts in VTFET devices are provided. In one aspect, a VTFET device includes: a fin(s); a bottom source/drain region at a base of the fin(s); a gate stack alongside the fin(s); a top source/drain region present at a top of the fin(s); a bottom source/drain contact to the bottom source/drain region; and a gate contact to the gate stack, wherein the bottom source drain and gate contacts each includes a top portion having a width W1CONTACT over a bottom portion having a width W2CONTACT, wherein W2CONTACT<W1CONTACT, and wherein a sidewall along the top portion is discontinuous with a sidewall along the bottom portion. The bottom portion having the width W2CONTACT is present alongside the gate stack and the top source/drain region. A method of forming a VTFET device is also provided.

Abstract: A device includes: a first dielectric material; a first metal line in the first dielectric material; a second dielectric material disposed on the first dielectric material and the first metal line; a second metal line in the second dielectric material; and a plurality of metal vias disposed on a same level and connecting the first metal line and the second metal line, wherein the plurality of metal vias comprise a first top via and a bottom via having different sidewall profile angles.

Abstract: This disclosure is directed to a case of an electronic device having a box, an elastic arm, a first fastening structure, a second fastening structure, and a magnet. The box has a first housing and a second housing closed with the first housing. The elastic arm is arranged in the first housing, the elastic arm is located at one side of the first housing, and at least a portion of the elastic arm is extended beyond an edge of the first housing. The first fastening structure is disposed on the elastic arm and located beyond the edge of the first housing. The second fastening structure is arranged on an internal surface at one side of the second housing, and the first fastening structure and the second fastening structure are buckled with each other. The magnet is arranged on the spring arm.

Abstract: Semiconductor devices and methods of forming the same include forming dummy gate spacers in a trench in a semiconductor substrate. A dummy gate is formed in the trench. An exposed dummy gate spacer is replaced with a sacrificial spacer. A cap layer is formed over the dummy gate. The cap layer is etched to expose the dummy gate. The sacrificial spacer is replaced with an isolation dielectric spacer. The dummy gate is replaced with a conductor.

Abstract: An operation method for a memory device is provided. A memory block of the memory device includes an array of memory cells including cell strings and cell pages. Serially numbered and arranged bit lines are connected to the cell strings, respectively. Serially numbered and arranged word lines are connected to the cell pages, respectively. The operation method includes: performing a batch writing to each of the cell pages, such that the memory cells in each cell page are respectively grouped as an earlier written memory cell or a later written memory cell, depending on the connected bit line is either even-numbered or odd-numbered. Each cell page has a respective write sequence. In terms of write sequence, each cell page is identical with one of 2 nearest cell pages, and opposite to the other of the 2 nearest cell pages.

Abstract: A device and method for detecting an inter-turn electromagnetic pulse vibration wave characteristic of a turbogenerator rotor winding are provided. A signal source and a time sequence control circuit generate a high-potential abrupt electric field; circularly polarized electromagnetic waves generated by a parasitic inductive power supply and symmetrically deflecting by 180° are respectively coupled to a positive electrode and a negative electrode clockwise or counter-clockwise; a first turn on the positive electrode and a first turn on the negative electrode are mutually induced; as time goes by, energy is returned to the parasitic inductive power supply, and is sequentially conducted to a second turn; the parasitic inductive power supply and the second turn further start feeding back energy to the first turn in circular polarization; all turns sequentially perform feedback and superposition one another stage by stage; and all coupling turns show sinusoidal waves with a same time constant.

Abstract: A device and method for detecting an inter-turn electromagnetic pulse vibration wave characteristic of a turbogenerator rotor winding are provided. A signal source and a time sequence control circuit generate a high-potential abrupt electric field; circularly polarized electromagnetic waves generated by a parasitic inductive power supply and symmetrically deflecting by 180° are respectively coupled to a positive electrode and a negative electrode clockwise or counter-clockwise; a first turn on the positive electrode and a first turn on the negative electrode are mutually induced; as time goes by, energy is returned to the parasitic inductive power supply, and is sequentially conducted to a second turn; the parasitic inductive power supply and the second turn further start feeding back energy to the first turn in circular polarization; all turns sequentially perform feedback and superposition one another stage by stage; and all coupling turns show sinusoidal waves with a same time constant.

Abstract: Semiconductor devices and methods of forming the same include a lower semiconductor device over a substrate, the lower semiconductor device having a first width. An upper semiconductor device is over the lower semiconductor device. The upper semiconductor device has a second width smaller than the first width. A dielectric structure is over the lower semiconductor device and has a first sidewall that faces the upper semiconductor device and a second sidewall that aligns vertically with a sidewall of the lower semiconductor device.

Abstract: A semiconductor structure is presented including semiconductor layers of a first nanosheet stack, semiconductor layers of a second nanosheet stack formed over and having a stepped nanosheet formation with respect to the semiconductor layers of the first nanosheet stack, a first epitaxial growth formed adjacent the semiconductor layers of the first nanosheet stack, and a second epitaxial growth formed adjacent the semiconductor layers of the second nanosheet stack such that the second epitaxial growth has a stepped formation with respect to the first epitaxial growth. The second epitaxial growth has a volume greater than a volume of the first epitaxial growth.

Abstract: Embodiments of the invention include a stacked device having a first epitaxial region and a second epitaxial region vertically displaced from the first epitaxial region. The first epitaxial region comprising an asymmetric profile with a horizontal protrusion.

Abstract: A semiconductor device includes a first transistor and a first gate electrically coupled to the first transistor. A second transistor is positioned on top of the first transistor. A second gate is electrically coupled to the second transistor. A dielectric isolation layer is positioned between the first gate and the second gate. A first conductive contact is electrically coupled to the first gate. A second conductive contact is electrically coupled to the second gate. A control of the first gate through the first conductive contact is independent of a control of the second gate through the second conductive contact.

Abstract: A semiconductor structure is presented including a plurality of field effect transistor (FET) devices, each FET device having a different gate threshold voltage, first spacers disposed on sidewalls of each FET device, second spacers disposed over and in direct contact with the first spacers, the second spacers having a width greater than a width of the first spacers, and a gate contact directly contacting an FET device of the plurality of FET devices, where only an upper portion of the gate contact directly contacts third spacers on opposed ends thereof. The second spacers can have a bi-layer configuration and the gate contact wraps around a top portion of the FET device in direct contact with the gate contact.

Abstract: A semiconductor device includes a nanostructure field effect transistor (FET). The FET includes a gate and a first source or drain (S/D) region. A frontside S/D contact may be connected to and extends vertically upward from a top surface of the first S/D region. The FET further includes a second S/D region. The second S/D region extends below a bottom surface of the gate. A backside S/D contact may be connected to and extend vertically downward from a bottom surface of the second S/D region.

Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a gate and a first source or drain (S/D) region. A frontside S/D contact may be connected to and extend vertically upward from a top surface of the first S/D region. The FET further includes a second S/D region. The second S/D region includes a conduit liner and an inner column internal to the conduit liner that extends below a bottom surface of the wraparound gate. A backside S/D contact may be connected to and extend vertically downward from a bottom surface of the second S/D region.