Abstract: A high aspect ratio contact structure formed within a dielectric material includes a top portion and a bottom portion. The top portion of the contact structure includes a tapering profile towards the bottom portion. A first metal stack surrounded by an inner spacer is located within the top portion of the contact structure and a second metal stack is located within the bottom portion of the contact structure. A width of the bottom portion of the contact structure is greater than a minimum width of the top portion of the contact structure.

Abstract: A structure including a first semiconductor die and a second semiconductor die is provided. The first semiconductor die includes a first bonding structure. The first bonding structure includes a first dielectric layer and first conductors embedded in the first dielectric layer. The second semiconductor die includes a second bonding structure. The second bonding structure includes a second dielectric layer and second conductors embedded in the second dielectric layer. The first dielectric layer is in contact with the second dielectric layer, and the first conductors are in contact with the second conductors. Thermal conductivity of the first dielectric layer and the second dielectric layer is greater than thermal conductivity of silicon dioxide.

Abstract: An operation method for a memory device is provided. A memory block of the memory device includes an array of memory cells including cell strings and cell pages. Serially numbered and arranged bit lines are connected to the cell strings, respectively. Serially numbered and arranged word lines are connected to the cell pages, respectively. The operation method includes: performing a batch writing to each of the cell pages, such that the memory cells in each cell page are respectively grouped as an earlier written memory cell or a later written memory cell, depending on the connected bit line is either even-numbered or odd-numbered. Each cell page has a respective write sequence. In terms of write sequence, each cell page is identical with one of 2 nearest cell pages, and opposite to the other of the 2 nearest cell pages.

Abstract: A semiconductor includes a substrate. A gate structure is disposed on the substrate. A liner oxide contacts a side of the gate structure. A silicon oxide spacer contacts the liner oxide. An end of the silicon oxide spacer forms a kink profile. A silicon nitride spacer contacts the silicon oxide spacer and a tail of the silicon nitride spacer covers part of the kink profile. A stressor covers the silicon nitride spacer and the substrate.

Abstract: A method for federated data query includes: using, by a first electronic device, a joint query statement corresponding to a federated data query to obtain at least one operator containing a joint query operator; transforming the joint query operator to a first joint security operator; determining first data for intersection on the first electronic device by executing the first joint security operator, receiving second data for intersection from a second electronic device involved in the federated data query, and performing joint computing on the first data for intersection and the second data for intersection in a form of a ciphertext to obtain a joint data table; and determining a federated data query result corresponding to the at least one operator based on the joint data table.

Abstract: Embodiments disclosed herein describe methods of forming semiconductor devices. The methods may include etching vias and trenches in a middle-of-line (MOL) layer that has a low-k dielectric layer, a sacrificial nitride layer, and a hard mask layer. The methods may also include depositing a thin nitride layer within the via trench, depositing a carbon layer on the thin nitride layer within the vias and trenches, etching back the thin nitride layer to expose a portion of the hard mask layer, removing the hard mask layer and the carbon layer, and removing the thin nitride layer and the sacrificial nitride layer.

Abstract: The present application provides a digital twin utility tunnel system based on a reduced-order simulation model and a real-time calibration algorithm. The system includes a big data aggregation unit and a real-time simulation deduction unit. The big data aggregation unit is configured to collect static attribute data and real-time dynamic data. The real-time dynamic data includes fixed monitoring data and mobile monitoring data. The fixed monitoring data is collected by gas sensors fixedly installed in the utility tunnel, and the mobile monitoring data is collected by mobile sensors in the utility tunnel. The real-time simulation deduction unit includes a forward prediction module and an inversion calibration module.

Abstract: A method of forming stacked vertical field effect devices is provided. The method includes forming a layer stack on a substrate, wherein the layer stack includes a first spacer layer on the substrate, a first protective liner on the first spacer layer, a first gap layer on the first protective liner, a second protective liner on the first gap layer, a second spacer layer on the second protective liner, a sacrificial layer on the second spacer layer, a third spacer layer on the sacrificial layer, a third protective liner on the third spacer layer, a second gap layer on the third protective liner, a fourth protective liner on the second gap layer, and a fourth spacer layer on the fourth protective liner. The method further includes forming channels through the layer stack, a liner layer on the sidewalls of the channels, and a vertical pillar in the channels.

Abstract: A semiconductor chiplet device includes a package substrate, an interposer layer, a first die and a second die. The first die includes a first interface, and the second die includes a second interface. A first side of the interposer layer is configured to arrange the first die and the second die. The first die and the second die perform a data transmission through the first interface, the interposer layer and the second interface. The package substrate is arranged on a second side of the interposer layer, and includes a decoupling capacitor. The decoupling capacitor is arranged between the first interface and the second interface, or arranged in a vertical projection area of the first interface and the second interface on the package substrate.

Abstract: The present disclosure relates to an electronic device and a method for positioning. An electronic device used with a base station is disclosed, comprising a processing circuit configured to: cause a first set of intelligent surfaces to reflect a set of first reflected beams to be used for a first beam scanning with a user equipment (UE); cause a second set of intelligent surfaces to reflect a set of second reflected beams to be used for a second beam scanning with the UE, wherein the second set of intelligent surfaces is selected from the first set of intelligent surfaces, and a beam width for the set of second reflected beams is smaller than a beam width for the set of first reflected beams; and determine a position of the UE, based at least in part on a result of the second beam scanning.

Abstract: An electronic device includes a processing circuit configured to: measure the channel quality of multiple beams of a mobile large intelligent surface (LIS) and the channel quality of multiple beams of one or more candidate fixed LISs; and determine a fixed LIS, a service beam of the fixed LIS, and a service beam of the mobile LIS according to a measurement result, so as to provide service for the electronic device by the service beam of the fixed LIS and the service beam of the mobile LIS. According to the electronic device, the wireless communication method, and the computer-readable storage medium of the present disclosure, the advantages of the fixed LIS and the mobile LIS can be combined, and the fixed LIS and the mobile LIS can jointly provide service for a user equipment, so as to improve the communication quality of the user equipment.

Abstract: Disclosed in the present invention is an application of lysine (K)-specific demethylase 6B (KDM6B) in regulating and controlling the function of a mesenchymal stem cell. WDR5 is a co-binding protein for negatively regulating and controlling the functions of KDM6B and the MLL1. WDR5 can form a protein complex with KDM6B to inhibit the function of KDM6B, such that expression and functions of genes are regulated and controlled by regulating and controlling the methylation state of downstream senescence and osteogenesis related genes and gene promoter region histone, and finally the effects of regulating stem cell senescence and differentiation functions and bone/tooth tissue repair and regeneration functions are achieved. For a KDM6B and WDR5 binding region sequence, small-molecule polypeptide is researched, developed, and utilized, and the function of the mesenchymal stem cell is regulated by regulating and controlling the binding of a KDM6B/WDR5 complex.

Abstract: A sealing structure includes a box body and a cover body. The box body includes a plurality of side walls respectively including a plurality of outer and inner portions, an annular groove formed on the inner portions, and an annular protrusion portion. Each outer portion has a level difference with the corresponding inner portion. Any two adjacent ones of the side walls form a corner portion. An outer surface of each corner portion forms a sharp corner. The annular groove is arc-shaped at a position corresponding to each corner portion. Each corner portion includes a hollowed-out area. The cover body includes a main body in a polygonal shape with sharp corners, an annular protrusion portion protruding from the main body, and an annular groove. The annular protrusion portions extend into the annular grooves, so that the cover body is sealedly joined to the box body.

Abstract: The present application provides a digital twin utility tunnel system based on a reduced-order simulation model and a real-time calibration algorithm. The system includes a big data aggregation unit and a real-time simulation deduction unit. The big data aggregation unit is configured to collect static attribute data and real-time dynamic data. The real-time dynamic data includes fixed monitoring data and mobile monitoring data. The fixed monitoring data is collected by gas sensors fixedly installed in the utility tunnel, and the mobile monitoring data is collected by mobile sensors in the utility tunnel. The real-time simulation deduction unit includes a forward prediction module and an inversion calibration module.

Abstract: Techniques for area scaling of contacts in VTFET devices are provided. In one aspect, a VTFET device includes: a fin(s); a bottom source/drain region at a base of the fin(s); a gate stack alongside the fin(s); a top source/drain region present at a top of the fin(s); a bottom source/drain contact to the bottom source/drain region; and a gate contact to the gate stack, wherein the bottom source drain and gate contacts each includes a top portion having a width W1CONTACT over a bottom portion having a width W2CONTACT, wherein W2CONTACT<W1CONTACT, and wherein a sidewall along the top portion is discontinuous with a sidewall along the bottom portion. The bottom portion having the width W2CONTACT is present alongside the gate stack and the top source/drain region. A method of forming a VTFET device is also provided.

Abstract: A device includes: a first dielectric material; a first metal line in the first dielectric material; a second dielectric material disposed on the first dielectric material and the first metal line; a second metal line in the second dielectric material; and a plurality of metal vias disposed on a same level and connecting the first metal line and the second metal line, wherein the plurality of metal vias comprise a first top via and a bottom via having different sidewall profile angles.

Abstract: This disclosure is directed to a case of an electronic device having a box, an elastic arm, a first fastening structure, a second fastening structure, and a magnet. The box has a first housing and a second housing closed with the first housing. The elastic arm is arranged in the first housing, the elastic arm is located at one side of the first housing, and at least a portion of the elastic arm is extended beyond an edge of the first housing. The first fastening structure is disposed on the elastic arm and located beyond the edge of the first housing. The second fastening structure is arranged on an internal surface at one side of the second housing, and the first fastening structure and the second fastening structure are buckled with each other. The magnet is arranged on the spring arm.

Abstract: Semiconductor devices and methods of forming the same include forming dummy gate spacers in a trench in a semiconductor substrate. A dummy gate is formed in the trench. An exposed dummy gate spacer is replaced with a sacrificial spacer. A cap layer is formed over the dummy gate. The cap layer is etched to expose the dummy gate. The sacrificial spacer is replaced with an isolation dielectric spacer. The dummy gate is replaced with a conductor.

Abstract: An operation method for a memory device is provided. A memory block of the memory device includes an array of memory cells including cell strings and cell pages. Serially numbered and arranged bit lines are connected to the cell strings, respectively. Serially numbered and arranged word lines are connected to the cell pages, respectively. The operation method includes: performing a batch writing to each of the cell pages, such that the memory cells in each cell page are respectively grouped as an earlier written memory cell or a later written memory cell, depending on the connected bit line is either even-numbered or odd-numbered. Each cell page has a respective write sequence. In terms of write sequence, each cell page is identical with one of 2 nearest cell pages, and opposite to the other of the 2 nearest cell pages.