Abstract: A display panel control method, a display mode of the display panel including a normal display mode and a partial highlight display mode, the control method including obtaining display information of a display area in the display panel in the partial highlight display mode, the display information including a grayscale displayed corresponding to each pixel, and a number of pixels displaying the corresponding grayscale; determining a target gamma curve based on the display information, a difference between a display brightness corresponding to the grayscale in the target gamma curve and a target display brightness required for the pixels to display the corresponding grayscale in the partial highlight display mode being within a predetermined range; and controlling the pixels in the display area to display based on the target gamma curve.

Abstract: A semiconductor chip package is described. The semiconductor chip package has a substrate. The substrate has side I/Os on the additional surface area of the substrate. The side I/Os are coupled to I/Os of a semiconductor chip within the semiconductor chip package. A cooling assembly has also been described. The cooling assembly has a passageway to guide a cable to connect to a semiconductor chip's side I/Os that are located between a base of a cooling mass and an electronic circuit board that is between a bolster plate and a back plate and that is coupled to second I/Os of the semiconductor chip through a socket that the semiconductor chip's package is plugged into.

Abstract: A polyurethane and a preparation method thereof are provided. The polyurethane is represented by Formula 1. The preparation method of the polyurethane includes performing an addition reaction between a polyester-polyether polyol represented by the Formula 4 and a di-isocyanate. The formed polyurethane has high elasticity and high moisture-permeable properties.

Abstract: An inverter-based comparator includes an output stage circuit including a P-type output transistor and an N-type output transistor; a first inverter having a first transition voltage with an input node coupled to an input voltage and an output node generating a first inverted voltage and coupled to a gate of the N-type output transistor; and a second inverter having a second transition voltage with an input node coupled to the input voltage and an output node generating a second inverted voltage and coupled to a gate of the P-type output transistor. The first inverter and the second inverter each includes an inverter that includes a first inverter branch composed of at least one first P-type transistor and at least one first N-type transistor; and a second inverter branch composed of at least one second P-type transistor, at least one second N-type transistor and at least two tuning switches.

Abstract: Drive tools having with gear trains that may be used to drive a plurality of fasteners simultaneously. The gear train may include a driving gear that drives a plurality of fastener driver gears, each of which is connected to a fastener driver. Each of the plurality of fastener drivers may be turned simultaneously by rotation of the driving gear, which may be used to turn a similar plurality of fasteners a desired number of turns so that a desired preload is achieved simultaneously.

Abstract: A semiconductor device includes a bottom electrode and a magnetic tunneling junction (MTJ) element over the bottom electrode. The MTJ element includes a top magnetic plate, a bottom magnetic plate, and a barrier layer between the top magnetic plate and the bottom magnetic plate. An edge portion of the bottom magnetic plate extends beyond sidewalls of the top magnetic plate. The semiconductor device also includes a spacer disposed on the sidewalls of the top magnetic plate but not on sidewalls of the bottom magnetic plate, and a top electrode over the top magnetic plate.

Abstract: A semiconductor device comprises a first conductive feature on a semiconductor substrate, a bottom electrode on the first conductive feature, a magnetic tunnel junction (MTJ) stack on the bottom electrode, and a top electrode on the MTJ stack. A spacer contacts a sidewall of the top electrode, a sidewall of the MTJ stack, and a sidewall of the bottom electrode. A conductive feature contacts the top electrode.

Abstract: A rapid and automatic virus imaging and analysis system includes (i) electron optical sub-systems (EOSs), each of which has a large field of view (FOV) and is capable of instant magnification switching for rapidly scanning a virus sample; (ii) sample management sub-systems (SMSs), each of which automatically loads virus samples into one of the EOSs for virus sample scanning and then unloads the virus samples from the EOS after the virus sample scanning is completed; (iii) virus detection and classification sub-systems (VDCSs), each of which automatically detects and classifies a virus based on images from the EOS virus sample scanning; and (iv) a cloud-based collaboration sub-system for analyzing the virus sample scanning images, storing images from the EOS virus sample scanning, and storing and analyzing machine data associated with the EOSs, the SMSs, and the VDCSs.

Abstract: Provided are a cover plate, a display module, and a display device. The cover plate includes: a cover plate base (10) and an anti-fingerprint film layer (11) disposed on a side of the cover plate base (10); and an electrostatic transfer layer (20) disposed between the cover plate base (10) and the anti-fingerprint film layer (11) or disposed on a side of the cover plate base (10) facing away from the anti-fingerprint film layer (11).

Abstract: This disclosure is directed to a case of an electronic device having a box, an elastic arm, a first fastening structure, a second fastening structure, and a magnet. The box has a first housing and a second housing closed with the first housing. The elastic arm is arranged in the first housing, the elastic arm is located at one side of the first housing, and at least a portion of the elastic arm is extended beyond an edge of the first housing. The first fastening structure is disposed on the elastic arm and located beyond the edge of the first housing. The second fastening structure is arranged on an internal surface at one side of the second housing, and the first fastening structure and the second fastening structure are buckled with each other. The magnet is arranged on the spring arm.

Abstract: A large-scale in-situ dewatering treatment method and device for lake sludge are provided. The large-scale in-situ dewatering treatment method for lake sludge includes: step S1, sludge excavation: excavating sludge from a lake and transporting the sludge to a detention pond; step S2, in-situ detention: filtering the sludge in the detention pond to obtain filtered sludge; step S3, dewatering: transporting the filtered sludge to a dewatering workshop and performing deep dewatering on the filtered sludge to obtain mud blocks and wastewater; and step S4, environmental protection treatment: using the mud blocks to build an island near a dredging platform in the lake. The large-scale in-situ dewatering treatment method for lake sludge not only solves the problems of difficulty in selecting a temporary sludge disposal site and high capital investment costs in a traditional lake dredging operation, but also reduces the transportation cost of transporting sludge to a land.

Abstract: Semiconductor devices and methods of forming the same include forming dummy gate spacers in a trench in a semiconductor substrate. A dummy gate is formed in the trench. An exposed dummy gate spacer is replaced with a sacrificial spacer. A cap layer is formed over the dummy gate. The cap layer is etched to expose the dummy gate. The sacrificial spacer is replaced with an isolation dielectric spacer. The dummy gate is replaced with a conductor.

Abstract: An apparatus is described that includes an immersion bath chamber and a cover that is to seal the immersion bath chamber. An apparatus is described that includes an immersion bath chamber and an installable/removable transfer member. The installable/removable transfer member has fluidic connectors designed to couple to respective warmed fluid flow output ports of pluggable units to be cooled in the immersion bath chamber and having respective backplane interface designs. An apparatus is described that includes an immersion bath chamber and an overflow chamber. The overflow chamber is to receive an overflow of liquid coolant from the immersion bath chamber, wherein a first exit flow channel from the overflow chamber is coupled to a second exit fluid flow channel from the immersion bath chamber through a valve, wherein, an opening of the valve is controllable to vary a gravitational fluid flow within the immersion bath chamber.

Abstract: Provided are a benzimidazole compound as represented by formula (I) or a salt thereof, a preparation method therefor, and the use thereof. The benzimidazole compound or the salt thereof has excellent insecticidal and acaricidal effects, and can display acaricidal effects especially when same is used at a low concentration.

Abstract: A brightness adjustment method and a brightness adjustment device of a display panel and a display device are provided. The brightness adjustment method of the display panel including a plurality of sub-pixels includes acquiring grayscale data received by the display panel; performing a data processing process on the grayscale data and at least inserting a plurality of transitional grayscales between a 0-order grayscale and a 1st-order grayscale to form target grayscale data; and adjusting the brightness of the plurality of sub-pixels based on the target grayscale data.

Abstract: A semiconductor device comprises a first conductive feature on a semiconductor substrate, a bottom electrode on the first conductive feature, a magnetic tunnel junction (MTJ) stack on the bottom electrode, and a top electrode on the MTJ stack. A spacer contacts a sidewall of the top electrode, a sidewall of the MTJ stack, and a sidewall of the bottom electrode. A conductive feature contacts the top electrode.

Abstract: An operation method for a memory device is provided. A memory block of the memory device includes an array of memory cells including cell strings and cell pages. Serially numbered and arranged bit lines are connected to the cell strings, respectively. Serially numbered and arranged word lines are connected to the cell pages, respectively. The operation method includes: performing a batch writing to each of the cell pages, such that the memory cells in each cell page are respectively grouped as an earlier written memory cell or a later written memory cell, depending on the connected bit line is either even-numbered or odd-numbered. Each cell page has a respective write sequence. In terms of write sequence, each cell page is identical with one of 2 nearest cell pages, and opposite to the other of the 2 nearest cell pages.