Abstract: Semiconductor device layout designs for Vt tuning are provided. In one aspect, a semiconductor device is provided. The semiconductor device includes: at least one first metal line in contact with a source or drain of an FET; at least one second metal line in contact with a gate of the FET, wherein the first metal line crosses the second metal line; and an oxygen diffusion blocking layer on top of the at least one first metal line in an overlap area of the at least one first metal line and the at least one second metal line. A method of forming a semiconductor device is also provided.

Abstract: A method of forming stacked fin field effect devices is provided. The method includes forming a layer stack on a substrate, wherein the layer stack includes a first semiconductor layer on a surface of the substrate, a second semiconductor layer on the first semiconductor layer, a third semiconductor layer on the second semiconductor layer, a separation layer on the third semiconductor layer, a fourth semiconductor layer on the separation layer, a fifth semiconductor layer on the fourth semiconductor layer, and a sixth semiconductor layer on the fifth semiconductor layer. The method further includes forming a plurality of channels through the layer stack to the surface of the substrate, and removing portions of the second semiconductor layer and fifth semiconductor layer to form lateral grooves.

Abstract: Embodiments of the invention include a method of forming a multi-layer integrated circuit (IC) structure that includes forming a first layer of the multi-layered IC structure, wherein the first layer includes a trench having a liner and a conductive interconnect formed in the trench. The liner is formed such that it is not on a portion of a sidewall of the conductive interconnect. A multi-segmented cap is formed having a first cap segment and a second cap segment. The first cap segment is on a top surface of the conductive interconnect, and a first portion of the second cap segment is on the portion of the sidewall of the conductive interconnect. The second cap segment is on a top surface of the first cap segment.

Abstract: Embodiments of the invention include a method of forming a multi-layer integrated circuit (IC) structure that includes forming a first layer of the multi-layered IC structure, wherein the first layer includes a trench having a liner and a conductive interconnect formed in the trench. The liner is formed such that it is not on a portion of a sidewall of the conductive interconnect. A multi-segmented cap is formed having a first cap segment and a second cap segment. The first cap segment is on a top surface of the conductive interconnect, and a first portion of the second cap segment is on the portion of the sidewall of the conductive interconnect. The second cap segment is on a top surface of the first cap segment.

Abstract: A semiconductor device includes a first interconnect structure formed in an MX level of the semiconductor device, the MX level includes a third interlevel dielectric layer located above a second capping layer, a first trench within the third interlevel dielectric layer extending through the second capping layer to expose a top surface of a contact structure located below the second capping layer, the contact structure is located within a second interlevel dielectric layer, a second metal liner conformally deposited within the first trench, and a first seed layer conformally deposited above the second metal liner, the first seed layer includes a metal manganese film. A first thermal annealing process is conducted on the semiconductor device to form a first barrier liner underneath the second metal liner to prevent diffusion of conductive metals.

Abstract: A method for manufacturing a semiconductor device includes forming a first vertical transistor structure in a first device region on a substrate, and forming a second vertical transistor structure in a second device region on the substrate. The first vertical transistor structure includes a first plurality of fins, and the second vertical transistor structure includes a second plurality of fins. A plurality of first source/drain regions are grown from upper portions of the first plurality of fins, and a contact liner layer is formed on the first source/drain regions. The method further includes forming a plurality of first silicide portions from the contact liner layer on the first source/drain regions, and forming a plurality of second silicide portions on a plurality of second source/drain regions extending from upper portions of the second plurality of fins. The second silicide portions have a different composition than the first silicide portions.

Abstract: A method is presented for forming a self-aligned middle-of-the-line (MOL) contact. The method includes forming a fin structure over a substrate, depositing and etching a first set of dielectric layers over the fin structure, etching the fin structure to form a sacrificial fin and a plurality of active fins, depositing a work function metal layer over the plurality of active fins, depositing an inter-layer dielectric (ILD) and a second set of dielectric layers. The method further includes etching the second set of dielectric layers and the ILD to form a first via portion and to expose a top surface of the sacrificial fin, removing the sacrificial fin to form a second via portion, and filling the first and second via portions with a conductive material to form the MOL contact in the first via portion and a contact landing in the second via portion.

Abstract: A rotary cutting module for a paper cutting device has a roller and a paper-cutting blade. The roller extends along a rotating axis. A blade mount and multiple dynamic balancing recess sets are formed on an outer circumferential surface of the roller. The dynamic balancing recess sets are disposed apart from each other along the rotating axis. Each one of the dynamic balancing recess sets has multiple balancing recesses annularly disposed apart from each other. A depth of one of the balancing recesses of one of the dynamic balancing recess sets is different from a depth of one of the balancing recesses of another one of the dynamic balancing recess sets. Center of mass of each axial segment of the rotary cutting module can be adjusted individually to mitigate couple unbalance, thereby mitigating dynamic unbalance.

Abstract: A method includes forming a p-type field effect transistor region and an n-type field effect transistor region into a semiconductor substrate. The method implements a process flow to fabricate highly doped top source/drains with minimal lithography and etching processes. The method permits the formation of VFETs with increased functionality and reduced scaling.

Abstract: A method for fabricating a semiconductor device includes forming top source/drain contact material on top source/drain material disposed on one or more fins of a base structure, and subtractively patterning the top source/drain contact material to form at least one top source/drain contact. The at least one top source/drain contact has a positive tapered geometry. The method further includes cutting exposed end portions of the top source/drain material to form at least one top source/drain region underneath the at least one top source/drain contact.

Abstract: Provided are embodiments for an MOL interconnect structure having low metal-to-metal interface resistance interconnect structure including one or more contacts of one or more devices formed on a substrate. A dielectric layer is formed on one or more devices. One or more trenches are formed in the dielectric layer. The MOL interconnect structure also includes a barrier layer formed on one or more portions of the dielectric layer, along with a metallization layer, wherein the metallization layer forms a metal-to-metal interface with the one or more contacts.

Abstract: Semiconductor devices and methods of forming the same include forming a gate stack in contact with sidewalls of a semiconductor fin and on a bottom spacer over a bottom source/drain region. An encapsulating material is selectively deposited over the gate stack, leaving the bottom spacer exposed. An inter-layer dielectric is formed over the encapsulating material. A via is formed in the inter-layer dielectric to contact the bottom source/drain layer.

Abstract: A method of forming a semiconductor structure includes the following steps. At least a first source/drain region and a second source/drain region are formed in a substrate. At least a first sacrificial layer and a second sacrificial layer are respectively formed over the first source/drain region and the second source/drain region. A spacer layer is formed on at least a top surface of the substrate and around sides of the first sacrificial layer and the second sacrificial layer. The spacer layer includes an electrical-isolating material. The first sacrificial layer and a second sacrificial layer are removed to form a first open trench and a second open trench. The first open trench and the second open trench are filled with metal contact material to form a first metal contact and a second metal contact electrically isolated from each other by the spacer layer.

Abstract: A method of display user movement in a computing device of a virtual reality system is disclosed. The method comprises generating a first image in a first-person perspective with a first-person control, simulating an avatar according to a first control signal received from a controller of the virtual reality system, and generating a second image including the avatar in the first-person perspective with a third-person control, wherein the first-person perspective indicates that a user sees images as if seen through the avatar's eyes, and a field of view of the avatar is controlled by the user, the first-person control indicates that a user's movement is displayed by a relative position between the avatar and a scene of the images, and the third-person control indicates that the user's movement is displayed by different locations of the avatar in the images.

Abstract: The present disclosure relates to an automatically adjustable smart shelf, a cargo storing method, and an unmanned logistics system. The automatically adjustable smart shelf includes a shelf outer frame and a control unit. A first movable shelf layer and a second movable shelf layer provided on the shelf outer frame and respectively movable along a first direction and a second direction intersecting with each other. A control unit can control the first movable shelf layer and the second movable shelf layer to move along the first direction and the second direction respectively, so as to form various sizes of storage space for storing various cargos accordingly.

Abstract: A semiconductor device includes a first interconnect structure formed in an Mx level of the semiconductor device, the Mx level includes a third interlevel dielectric layer located above a second capping layer, a first trench within the third interlevel dielectric layer extending through the second capping layer to expose a top surface of a contact structure located below the second capping layer, the contact structure is located within a second interlevel dielectric layer, a second metal liner conformally deposited within the first trench, and a first seed layer conformally deposited above the second metal liner, the first seed layer includes a metal manganese film. A first thermal annealing process is conducted on the semiconductor device to form a first barrier liner underneath the second metal liner to prevent diffusion of conductive metals.

Abstract: The present disclosure relates to a distribution station for serving an unmanned logistics distribution vehicle and distribution method.

Abstract: A method includes applying a first dielectric material onto a semiconductor substrate to form a first dielectric layer on the semiconductor substrate, creating a plurality of openings in the dielectric layer, depositing a sacrificial material within the openings of the dielectric layer, removing the sacrificial material from at least a first segment of a first trench of the openings, depositing a second dielectric fill material into the first segment of the first trench opening where the sacrificial material was removed, removing the sacrificial material from at least some of the remaining openings and depositing a metallic material within the first trench opening to define at least first and second lines in the first trench and form a metallic interconnect structure.

Abstract: A method of forming stacked vertical field effect devices is provided. The method includes forming a layer stack on a substrate, wherein the layer stack includes a first spacer layer on the substrate, a first protective liner on the first spacer layer, a first gap layer on the first protective liner, a second protective liner on the first gap layer, a second spacer layer on the second protective liner, a sacrificial layer on the second spacer layer, a third spacer layer on the sacrificial layer, a third protective liner on the third spacer layer, a second gap layer on the third protective liner, a fourth protective liner on the second gap layer, and a fourth spacer layer on the fourth protective liner. The method further includes forming channels through the layer stack, a liner layer on the sidewalls of the channels, and a vertical pillar in the channels.