Patents by Inventor Chen Fan

Chen Fan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • LINER AND CAP STRUCTURES FOR REDUCING LOCAL INTERCONNECT VERTICAL RESISTANCE WITHOUT COMPROMISING RELIABILITY
    Publication number: 20200090990
    Abstract: Embodiments of the invention are directed to an interconnect stack including a first dielectric layer, a first trench formed in the first dielectric layer, and a first liner deposited in the first trench, wherein the first liner defines a second trench. A first conductive material is in the second trench and deposited over the first dielectric layer and the first conductive material. A third trench extends through the second dielectric layer and is over the first conductive material. A bottom surface of the third trench includes at least a portion of the top surface of the first conductive material. A second liner is in the third trench, on sidewalls of the third trench, and also on the portion of the top surface of the first conductive material. The second liner functions as a cap region configured to counter electro-migration or surface migration of the first conductive material.
    Type: Application
    Filed: November 15, 2019
    Publication date: March 19, 2020
    Inventors: Su Chen Fan, Hemanth Jagannathan, Raghuveer R. Patlolla, Cornelius Brown Peethala
  • LINER AND CAP STRUCTURES FOR REDUCING LOCAL INTERCONNECT VERTICAL RESISTANCE WITHOUT COMPROMISING RELIABILITY
    Publication number: 20200090989
    Abstract: Embodiments of the invention are directed to an interconnect stack including a first dielectric layer, a first trench formed in the first dielectric layer, and a first liner deposited in the first trench, wherein the first liner defines a second trench. A first conductive material is in the second trench and deposited over the first dielectric layer and the first conductive material. A third trench extends through the second dielectric layer and is over the first conductive material. A bottom surface of the third trench includes at least a portion of the top surface of the first conductive material. A second liner is in the third trench, on sidewalls of the third trench, and also on the portion of the top surface of the first conductive material. The second liner functions as a cap region configured to counter electro-migration or surface migration of the first conductive material.
    Type: Application
    Filed: September 18, 2018
    Publication date: March 19, 2020
    Inventors: Su Chen Fan, Hemanth Jagannathan, Raghuveer R. Patlolla, Cornelius Brown Peethala
  • LOW-RESISTANCE TOP CONTACT ON VTFET
    Publication number: 20200075746
    Abstract: A semiconductor includes a semiconductor substrate having a bottom source/drain region and a vertical semiconductor fin having a bottom end that contacts the semiconductor substrate. The semiconductor device further includes a top source/drain region on a top end of the vertical semiconductor. The top source/drain region is separated from the semiconductor substrate by the vertical semiconductor fin. The semiconductor device further includes an electrically conductive cap on an outer surface of the top source/drain region.
    Type: Application
    Filed: August 30, 2018
    Publication date: March 5, 2020
    Inventors: Christopher J. Waskiewicz, Su Chen Fan, Hari Prasad Amanapu, Hemanth Jagannathan
  • SELF-ALIGNED CONTACT FOR VERTICAL FIELD EFFECT TRANSISTOR
    Publication number: 20200052096
    Abstract: Embodiments of the invention are directed to a method and resulting structures for a semiconductor device having self-aligned contacts. In a non-limiting embodiment of the invention, a semiconductor fin is formed vertically extending from a bottom source/drain region of a substrate. A conductive gate is formed over a channel region of the semiconductor fin. A top source/drain region is formed on a surface of the semiconductor fin and a top metallization layer is formed on the top source/drain region. A dielectric cap is formed over the top metallization layer.
    Type: Application
    Filed: October 17, 2019
    Publication date: February 13, 2020
    Inventors: Brent A. Anderson, Steven Bentley, Su Chen Fan, Balasubramanian Pranatharthiharan, Junli Wang, Ruilong Xie
  • THREE-DIMENSIONAL FIELD EFFECT DEVICE
    Publication number: 20200035824
    Abstract: A method of forming stacked fin field effect devices is provided. The method includes forming a layer stack on a substrate, wherein the layer stack includes a first semiconductor layer on a surface of the substrate, a second semiconductor layer on the first semiconductor layer, a third semiconductor layer on the second semiconductor layer, a separation layer on the third semiconductor layer, a fourth semiconductor layer on the separation layer, a fifth semiconductor layer on the fourth semiconductor layer, and a sixth semiconductor layer on the fifth semiconductor layer. The method further includes forming a plurality of channels through the layer stack to the surface of the substrate, and removing portions of the second semiconductor layer and fifth semiconductor layer to form lateral grooves.
    Type: Application
    Filed: October 3, 2019
    Publication date: January 30, 2020
    Inventors: Huimei Zhou, Su Chen Fan, Shogo Mochizuki, Peng Xu, Nicolas J. Loubet
  • THREE-DIMENSIONAL FIELD EFFECT DEVICE
    Publication number: 20200035823
    Abstract: A method of forming stacked fin field effect devices is provided. The method includes forming a layer stack on a substrate, wherein the layer stack includes a first semiconductor layer on a surface of the substrate, a second semiconductor layer on the first semiconductor layer, a third semiconductor layer on the second semiconductor layer, a separation layer on the third semiconductor layer, a fourth semiconductor layer on the separation layer, a fifth semiconductor layer on the fourth semiconductor layer, and a sixth semiconductor layer on the fifth semiconductor layer. The method further includes forming a plurality of channels through the layer stack to the surface of the substrate, and removing portions of the second semiconductor layer and fifth semiconductor layer to form lateral grooves.
    Type: Application
    Filed: October 3, 2019
    Publication date: January 30, 2020
    Inventors: Huimei Zhou, Su Chen Fan, Shogo Mochizuki, Peng Xu, Nicolas J. Loubet
  • Gate tie-down enablement with inner spacer
    Patent number: 10522654
    Abstract: A gate tie-down structure includes a gate structure including a gate conductor and gate spacers and inner spacers formed on the gate spacers. Trench contacts are formed on sides of the gate structure. An interlevel dielectric (ILD) has a thickness formed over the gate structure. A horizontal connection is formed within the thickness of the ILD over an active area connecting the gate conductor and one of the trench contacts over one of the inner spacers.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: December 31, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC
    Inventors: Su Chen Fan, Andre P. Labonte, Lars W. Liebmann, Sanjay C. Mehta
  • Vertical field effect transistor with self-aligned contacts
    Patent number: 10497798
    Abstract: A vertical FinFET includes a semiconductor fin formed over a semiconductor substrate. A self-aligned first source/drain contact is electrically separated from a second source/drain contact by a sidewall spacer that is formed over an endwall of the fin. The sidewall spacer, which comprises a dielectric material, allows the self-aligned first source/drain contact to be located in close proximity to an endwall of the fin and the associated second source/drain contact without risk of an electrical short between the adjacent contacts.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: December 3, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Steven Bentley, Puneet Harischandra Suvarna, Chanro Park, Min Gyu Sung, Lars Liebmann, Su Chen Fan, Brent Anderson
  • GATE TIE-DOWN ENABLEMENT WITH INNER SPACER
    Publication number: 20190363178
    Abstract: A gate tie-down structure includes a gate structure including a gate conductor and gate spacers and inner spacers formed on the gate spacers. Trench contacts are formed on sides of the gate structure. An interlevel dielectric (ILD) has a thickness formed over the gate structure. A horizontal connection is formed within the thickness of the ILD over an active area connecting the gate conductor and one of the trench contacts over one of the inner spacers.
    Type: Application
    Filed: August 9, 2019
    Publication date: November 28, 2019
    Inventors: Su Chen Fan, Andre P. Labonte, Lars W. Liebmann, Sanjay C. Mehta
  • Embedded bottom metal contact formed by a self-aligned contact process for vertical transistors
    Patent number: 10490653
    Abstract: Embodiments are directed to a method and resulting structures for a vertical field effect transistor (VFET) having an embedded bottom metal contact. A semiconductor fin is formed on a doped region of a substrate. A portion of the doped region adjacent to the semiconductor fin is recessed and an embedded contact is formed on the recessed portion. A material of the conductive rail is selected such that a conductivity of the embedded contact is higher than a conductivity of the doped region.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: November 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Su Chen Fan, Zuoguang Liu, Heng Wu, Tenko Yamashita
  • Three-dimensional field effect device
    Patent number: 10490667
    Abstract: A method of forming stacked fin field effect devices is provided. The method includes forming a layer stack on a substrate, wherein the layer stack includes a first semiconductor layer on a surface of the substrate, a second semiconductor layer on the first semiconductor layer, a third semiconductor layer on the second semiconductor layer, a separation layer on the third semiconductor layer, a fourth semiconductor layer on the separation layer, a fifth semiconductor layer on the fourth semiconductor layer, and a sixth semiconductor layer on the fifth semiconductor layer. The method further includes forming a plurality of channels through the layer stack to the surface of the substrate, and removing portions of the second semiconductor layer and fifth semiconductor layer to form lateral grooves.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: November 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Huimei Zhou, Su Chen Fan, Shogo Mochizuki, Peng Xu, Nicolas J. Loubet
  • THREE-DIMENSIONAL FIELD EFFECT DEVICE
    Publication number: 20190355845
    Abstract: A method of forming stacked fin field effect devices is provided. The method includes forming a layer stack on a substrate, wherein the layer stack includes a first semiconductor layer on a surface of the substrate, a second semiconductor layer on the first semiconductor layer, a third semiconductor layer on the second semiconductor layer, a separation layer on the third semiconductor layer, a fourth semiconductor layer on the separation layer, a fifth semiconductor layer on the fourth semiconductor layer, and a sixth semiconductor layer on the fifth semiconductor layer. The method further includes forming a plurality of channels through the layer stack to the surface of the substrate, and removing portions of the second semiconductor layer and fifth semiconductor layer to form lateral grooves.
    Type: Application
    Filed: May 15, 2018
    Publication date: November 21, 2019
    Inventors: Huimei Zhou, Su Chen Fan, Shogo Mochizuki, Peng Xu, Nicolas J. Loubet
  • THREE-DIMENSIONAL FIELD EFFECT DEVICE
    Publication number: 20190355717
    Abstract: A method of forming stacked vertical field effect devices is provided. The method includes forming a layer stack on a substrate, wherein the layer stack includes a first spacer layer on the substrate, a first protective liner on the first spacer layer, a first gap layer on the first protective liner, a second protective liner on the first gap layer, a second spacer layer on the second protective liner, a sacrificial layer on the second spacer layer, a third spacer layer on the sacrificial layer, a third protective liner on the third spacer layer, a second gap layer on the third protective liner, a fourth protective liner on the second gap layer, and a fourth spacer layer on the fourth protective liner. The method further includes forming channels through the layer stack, a liner layer on the sidewalls of the channels, and a vertical pillar in the channels.
    Type: Application
    Filed: May 15, 2018
    Publication date: November 21, 2019
    Inventors: Huimei Zhou, Su Chen Fan, Shogo Mochizuki, Peng Xu, Nicolas J. Loubet
  • Local interconnect structure including non-eroded contact via trenches
    Patent number: 10388602
    Abstract: A local interconnect structure includes a substrate having a dielectric layer and at least one semiconductor contact structure embedded in the dielectric layer. An electrically conductive material is deposited in a non-eroded contact trench that defines at least one electrically conducive contact via. The contact via extends from a first end that is flush with an upper surface of the dielectric layer to a second end that contacts the at one semiconductor contact structure. A local conductive material layer is formed in the dielectric layer and contacts the first end of the contact via. The non-eroded contact trench includes sharp upper corners formed at approximately ninety degrees with respect to the first end of the contact via.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: August 20, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Su Chen Fan, Vimal Kamineni, Andre P. Labonte, Ruilong Xie
  • VERTICAL FIELD EFFECT TRANSISTOR WITH SELF-ALIGNED CONTACTS
    Publication number: 20190252267
    Abstract: A vertical FinFET includes a semiconductor fin formed over a semiconductor substrate. A self-aligned first source/drain contact is electrically separated from a second source/drain contact by a sidewall spacer that is formed over an endwall of the fin. The sidewall spacer, which comprises a dielectric material, allows the self-aligned first source/drain contact to be located in close proximity to an endwall of the fin and the associated second source/drain contact without risk of an electrical short between the adjacent contacts.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 15, 2019
    Inventors: Ruilong Xie, Steven Bentley, Puneet Harischandra Suvarna, Chanro Park, Min Gyu Sung, Lars Liebmann, Su Chen Fan, Brent Anderson
  • Replacement metal gate stack for diffusion prevention
    Patent number: 10332971
    Abstract: A method of forming a semiconductor structure includes depositing a gate dielectric layer lining a recess of a gate structure formed on a substrate with a first portion of the gate dielectric layer covering sidewalls of the recess and a second portion of the gate dielectric layer covering a bottom of the recess. A protective layer is deposited above the gate dielectric layer and then recessed selectively to the gate dielectric layer so that a top surface of the protective layer is below of the recess. The first portion of the gate dielectric layer is recessed until a top of the first portion of the gate dielectric layer is approximately coplanar with the top surface of the protective layer. The protective layer is removed and a conductive barrier is deposited above the recessed first portion of the gate dielectric layer to cut a diffusion path to the gate dielectric layer.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: June 25, 2019
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Johnathan E. Faltermeier, Su Chen Fan, Sivananda K. Kanakasabapathy, Injo Ok, Tenko Yamashita
  • Gate tie-down enablement with inner spacer
    Patent number: 10332977
    Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: June 25, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC
    Inventors: Su Chen Fan, Andre P. Labonte, Lars W. Liebmann, Sanjay C. Mehta
  • Embedded bottom metal contact formed by a self-aligned contact process for vertical transistors
    Patent number: 10319835
    Abstract: Embodiments are directed to a method and resulting structures for a vertical field effect transistor (VFET) having an embedded bottom metal contact. A semiconductor fin is formed on a doped region of a substrate. A portion of the doped region adjacent to the semiconductor fin is recessed and an embedded contact is formed on the recessed portion. A material of the conductive rail is selected such that a conductivity of the embedded contact is higher than a conductivity of the doped region.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: June 11, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Su Chen Fan, Zuoguang Liu, Heng Wu, Tenko Yamashita
  • Method of forming vertical FinFET device having self-aligned contacts
    Patent number: 10312154
    Abstract: A vertical FinFET includes a semiconductor fin formed over a semiconductor substrate. A self-aligned first source/drain contact is electrically separated from a second source/drain contact by a spacer layer that is formed over an endwall of the fin. The spacer layer, which comprises a dielectric material, allows the self-aligned first source/drain contact to be located in close proximity to an endwall of the fin and the associated second source/drain contact without risk of an electrical short between the adjacent contacts.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: June 4, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Steven Bentley, Puneet Harischandra Suvarna, Chanro Park, Min Gyu Sung, Lars Liebmann, Su Chen Fan, Brent Anderson
  • SELF-ALIGNED CONTACTS FOR VERTICAL FIELD EFFECT TRANSISTOR CELL HEIGHT SCALING
    Publication number: 20190088764
    Abstract: A vertical FinFET includes a semiconductor fin formed over a semiconductor substrate. A self-aligned first source/drain contact is electrically separated from a second source/drain contact by a spacer layer that is formed over an endwall of the fin. The spacer layer, which comprises a dielectric material, allows the self-aligned first source/drain contact to be located in close proximity to an endwall of the fin and the associated second source/drain contact without risk of an electrical short between the adjacent contacts.
    Type: Application
    Filed: September 15, 2017
    Publication date: March 21, 2019
    Applicant: GLBOALFOUNDRIES INC.
    Inventors: Ruilong XIE, Steven BENTLEY, Puneet Harischandra SUVARNA, Chanro PARK, Min Gyu SUNG, Lars LIEBMANN, Su Chen FAN, Brent ANDERSON