Patents by Inventor Chen-Han Wang
Chen-Han Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11956972Abstract: A semiconductor memory device includes a substrate having a memory area and a logic circuit area thereon, a first interlayer dielectric layer on the substrate, and a second interlayer dielectric layer on the substrate. An embedded memory cell structure is disposed within the memory area between the first interlayer dielectric layer and the second interlayer dielectric layer. The second interlayer dielectric layer includes a first portion covering the embedded memory cell structure within the memory area and a second portion covering the logic circuit area. A top surface of the first portion is coplanar with a top surface of the second portion.Type: GrantFiled: April 13, 2021Date of Patent: April 9, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Si-Han Tsai, Ching-Hua Hsu, Chen-Yi Weng, Po-Kai Hsu
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Publication number: 20240099154Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.Type: ApplicationFiled: November 21, 2023Publication date: March 21, 2024Applicant: UNITED MICROELECTRONICS CORPInventors: Hui-Lin Wang, Si-Han Tsai, Dong-Ming Wu, Chen-Yi Weng, Ching-Hua Hsu, Ju-Chun Fan, Yi-Yu Lin, Che-Wei Chang, Po-Kai Hsu, Jing-Yin Jhang
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Patent number: 11917923Abstract: A magnetoresistive random access memory (MRAM) structure, including a substrate and multiple MRAM cells on the substrate, wherein the MRAM cells are arranged in a memory region adjacent to a logic region. An ultra low-k (ULK) layer covers the MRAM cells, wherein the surface portion of ultra low-k layer is doped with fluorine, and dents are formed on the surface of ultra low-k layer at the boundaries between the memory region and the logic region.Type: GrantFiled: April 28, 2021Date of Patent: February 27, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Ching-Hua Hsu, Si-Han Tsai, Shun-Yu Huang, Chen-Yi Weng, Ju-Chun Fan, Che-Wei Chang, Yi-Yu Lin, Po-Kai Hsu, Jing-Yin Jhang, Ya-Jyuan Hung
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Patent number: 11901220Abstract: The present disclosure relates to a method for forming a semiconductor device includes forming an opening between first and second sidewalls of respective first and second terminals. The first and second sidewalls oppose each other. The method further includes depositing a first dielectric material at a first deposition rate on top portions of the opening and depositing a second dielectric material at a second deposition rate on the first dielectric material and on the first and second sidewalls. The second dielectric material and the first and second sidewalls entrap a pocket of air. The method also includes performing a treatment process on the second dielectric material.Type: GrantFiled: July 23, 2020Date of Patent: February 13, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shuen-Shin Liang, Chen-Han Wang, Keng-Chu Lin, Tetsuji Ueno, Ting-Ting Chen
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Patent number: 11848238Abstract: The present disclosure describes a method of fabricating a semiconductor structure that includes forming a fin structure on a substrate, forming a polysilicon gate structure on a first portion of the fin structure, forming an opening in a second portion of the fin structure, wherein the first and second portions of the fin structure is adjacent to each other, forming a recess laterally on a sidewall of the first portion of the fin structure underlying the polysilicon gate structure, and forming an inner spacer structure within the recess. The inner spacer structure comprises an inner air spacer enclosed by a first dielectric spacer layer and a second dielectric spacer layer.Type: GrantFiled: June 30, 2020Date of Patent: December 19, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Han Wang, Keng-Chu Lin, Shuen-Shin Liang, Tetsuji Ueno, Ting-Ting Chen
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Publication number: 20230343873Abstract: Methods for manufacturing a semiconductor structure are provided. The method includes alternately stacking first semiconductor material layers and second semiconductor layers over a substrate and patterning the first semiconductor material layers and the second semiconductor layers to form a first fin structure and a second fin structure. The method also includes forming an insulating layer around the first fin structure and the second fin structure and forming a dielectric fin structure over the insulating layer and spaced apart from the first fin structure and the second fin structure. The method also includes forming a first source/drain structure attached to the first fin structure and forming a semiconductor layer covering the first source/drain structure. The method also includes oxidizing the semiconductor layer to form an oxide layer and forming a second source/drain structure attached to the second fin structure after the oxide layer is formed.Type: ApplicationFiled: June 29, 2023Publication date: October 26, 2023Inventors: Chen-Han WANG, Pei-Hsun WANG, Chun-Hsiung LIN, Chih-Hao WANG
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Publication number: 20230268422Abstract: A semiconductor device includes a semiconductor substrate, a channel region, a gate structure, two epitaxial structures, and two silicide structures. The channel region is disposed on the semiconductor substrate. The gate structure is disposed on the semiconductor substrate and over the channel region. The epitaxial structures are connected at opposite ends of the channel region and are disposed opposite to each other relative to the gate structure. The silicide structures respectively surround the epitaxial structures. A method of manufacturing a semiconductor device is also provided.Type: ApplicationFiled: February 18, 2022Publication date: August 24, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Han WANG, Keng-Chu LIN, Shuen-Shin LIANG
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Publication number: 20230268268Abstract: The present disclosure provides an interconnect structure and a method for forming an interconnect structure. The method for forming an interconnect structure includes forming a first interlayer dielectric (ILD) layer over a substrate, forming a contact in the first ILD layer, forming a second ILD layer over the first ILD layer, forming a first opening in the second ILD layer and obtaining an exposed side surface of the second ILD layer over the contact, forming a densified dielectric layer at the exposed side surface of the second ILD layer, including oxidizing the exposed side surface of the second ILD layer by irradiating a microwave on the second ILD layer, and forming a via in contact with the densified dielectric layer.Type: ApplicationFiled: April 24, 2023Publication date: August 24, 2023Inventors: KHADERBAD MRUNAL ABHIJITH, YU-YUN PENG, FU-TING YEN, CHEN-HAN WANG, TSU-HSIU PERNG, KENG-CHU LIN
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Publication number: 20230268387Abstract: The present disclosure relates to a semiconductor device including first and second terminals formed on a fin region and a seal layer formed between the first and second terminals. The seal layer includes a silicon carbide material doped with oxygen. The semiconductor device also includes an air gap surrounded by the seal layer, the fin region, and the first and second terminals.Type: ApplicationFiled: May 2, 2023Publication date: August 24, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shuen-Shin LIANG, Tetsuji UENO, Ting-Ting CHEN, Chen-Han WANG, Keng-Chu LIN
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Patent number: 11735666Abstract: Methods for manufacturing a semiconductor structure are provided. The semiconductor structure includes a substrate a substrate and channel layers vertically stacked over the substrate. The semiconductor structure also includes a dielectric fin structure formed adjacent to the channel layers and a gate structure abutting the channel layers and the dielectric fin structure. The semiconductor structure also includes a source/drain structure attached to the channel layers and a contact formed over the source/drain structure. The semiconductor structure also includes a Si layer covering a portion of a top surface of the source/drain structure. In addition, the Si layer is sandwiched between the dielectric fin structure and the contact.Type: GrantFiled: July 26, 2022Date of Patent: August 22, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Han Wang, Pei-Hsun Wang, Chun-Hsiung Lin, Chih-Hao Wang
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Publication number: 20230242115Abstract: The present disclosure describes a method of forming an intermediate spacer structure between a gate structure and a source/drain (S/D) contact structure and removing a top portion of the intermediate spacer structure to form a recess. The intermediate spacer structure includes a first spacer layer, a second spacer layer, and a sacrificial spacer layer between the first spacer layer and the second spacer layer. The method further includes removing the sacrificial spacer layer to form an air gap between the first spacer layer and the second spacer layer and spinning a dielectric layer on the air gap, the first spacer layer, and the second spacer layer to fill in the recess and seal the air gap. The dielectric layer includes raw materials for a spin-on dielectric material.Type: ApplicationFiled: April 10, 2023Publication date: August 3, 2023Applicant: Taiwan Semiconductor For Manufactuing Co., Ltd.Inventors: Ting-Ting CHEN, Chen-Han Wang, Keng-Chu Lin, Shuen-Shin Liang, Tsu-Hsiu Perng, Tsai-Jung Ho, Tsung-Han Ko, Tetsuji Ueno, Yahru Cheng
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Patent number: 11688766Abstract: The present disclosure relates to a semiconductor device including first and second terminals formed on a fin region and a seal layer formed between the first and second terminals. The seal layer includes a silicon carbide material doped with oxygen. The semiconductor device also includes an air gap surrounded by the seal layer, the fin region, and the first and second terminals.Type: GrantFiled: April 4, 2022Date of Patent: June 27, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shuen-Shin Liang, Chen-Han Wang, Keng-Chu Lin, Tetsuji Ueno, Ting-Ting Chen
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Patent number: 11637062Abstract: The present disclosure provides an interconnect structure and a method for forming an interconnect structure. The method for forming an interconnect structure includes forming a first interlayer dielectric (ILD) layer over a substrate, forming a contact in the first ILD layer, forming a second ILD layer over the first ILD layer, forming a first opening in the second ILD layer and obtaining an exposed side surface of the second ILD layer over the contact, forming a densified dielectric layer at the exposed side surface of the second ILD layer, including oxidizing the exposed side surface of the second ILD layer by irradiating a microwave on the second ILD layer, and forming a via in contact with the densified dielectric layer.Type: GrantFiled: February 21, 2022Date of Patent: April 25, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Khaderbad Mrunal Abhijith, Yu-Yun Peng, Fu-Ting Yen, Chen-Han Wang, Tsu-Hsiu Perng, Keng-Chu Lin
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Patent number: 11626482Abstract: The present disclosure describes a method of forming an intermediate spacer structure between a gate structure and a source/drain (S/D) contact structure and removing a top portion of the intermediate spacer structure to form a recess. The intermediate spacer structure includes a first spacer layer, a second spacer layer, and a sacrificial spacer layer between the first spacer layer and the second spacer layer. The method further includes removing the sacrificial spacer layer to form an air gap between the first spacer layer and the second spacer layer and spinning a dielectric layer on the air gap, the first spacer layer, and the second spacer layer to fill in the recess and seal the air gap. The dielectric layer includes raw materials for a spin-on dielectric material.Type: GrantFiled: March 4, 2021Date of Patent: April 11, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ting-Ting Chen, Chen-Han Wang, Keng-Chu Lin, Shuen-Shin Liang, Tsu-Hsiu Perng, Tsai-Jung Ho, Tsung-Han Ko, Tetsuji Ueno, Yahru Cheng
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Publication number: 20230038822Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The method includes forming first and second fin structures on a substrate, forming n- and p-type source/drain (S/D) regions on the first and second fin structures, respectively, forming first and second oxidation stop layers on the n- and p-type S/D regions, respectively, epitaxially growing first and second semiconductor layers on the first and second oxidation stop layers, respectively, converting the first and second semiconductor layers into first and second semiconductor oxide layers, respectively, forming a first silicide-germanide layer on the p-type S/D region, and forming a second silicide-germanide layer on the first silicide-germanide layer and on the n-type S/D region.Type: ApplicationFiled: June 6, 2022Publication date: February 9, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Han WANG, Keng-Chu LIN, Tsungyu HUNG
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Publication number: 20230043999Abstract: A method for estimating at least one electrical property of a semiconductor device is provided. The method includes forming the semiconductor device and at least one testing unit on a substrate, irradiating the testing unit with at least one electron beam, estimating electrons from the testing unit induced by the electron beam, and estimating the electrical property of the semiconductor device according to intensity of the estimated electrons from the testing unit.Type: ApplicationFiled: October 24, 2022Publication date: February 9, 2023Inventors: Chen-Han Wang, Chun-Hsiung Lin
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Publication number: 20220367278Abstract: The present disclosure describes a method of fabricating a semiconductor structure that includes forming a fin structure on a substrate, forming a polysilicon gate structure on a first portion of the fin structure, forming an opening in a second portion of the fin structure, wherein the first and second portions of the fin structure is adjacent to each other, forming a recess laterally on a sidewall of the first portion of the fin structure underlying the polysilicon gate structure, and forming an inner spacer structure within the recess. The inner spacer structure comprises an inner air spacer enclosed by a first dielectric spacer layer and a second dielectric spacer layer.Type: ApplicationFiled: July 27, 2022Publication date: November 17, 2022Applicant: Taiwan Semiconductor Manufafacturing Co, Ltd.Inventors: Chen-Han WANG, Keng-Chu LIN, Shuen-Shin LIANG, Tetsuji UENO, Ting-Ting CHEN
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Publication number: 20220367701Abstract: Methods for manufacturing a semiconductor structure are provided. The semiconductor structure includes a substrate a substrate and channel layers vertically stacked over the substrate. The semiconductor structure also includes a dielectric fin structure formed adjacent to the channel layers and a gate structure abutting the channel layers and the dielectric fin structure. The semiconductor structure also includes a source/drain structure attached to the channel layers and a contact formed over the source/drain structure. The semiconductor structure also includes a Si layer covering a portion of a top surface of the source/drain structure. In addition, the Si layer is sandwiched between the dielectric fin structure and the contact.Type: ApplicationFiled: July 26, 2022Publication date: November 17, 2022Inventors: Chen-Han WANG, Pei-Hsun WANG, Chun-Hsiung LIN, Chih-Hao WANG
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Patent number: 11502166Abstract: The present disclosure relates to a semiconductor device including first and second terminals formed on a fin region and a seal layer formed between the first and second terminals. The seal layer includes a silicon carbide material doped with oxygen. The semiconductor device also includes an air gap surrounded by the seal layer, the fin region, and the first and second terminals.Type: GrantFiled: November 20, 2020Date of Patent: November 15, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shuen-Shin Liang, Chen-Han Wang, Keng-Chu Lin, Tetsuji Ueno, Ting-Ting Chen
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Patent number: 11480606Abstract: A method for estimating at least one electrical property of a semiconductor device is provided. The method includes forming the semiconductor device and at least one testing unit on a substrate, irradiating the testing unit with at least one electron beam, estimating electrons from the testing unit induced by the electron beam, and estimating the electrical property of the semiconductor device according to intensity of the estimated electrons from the testing unit.Type: GrantFiled: June 14, 2016Date of Patent: October 25, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chen-Han Wang, Chun-Hsiung Lin