Patents by Inventor Chen-Hao LIEN

Chen-Hao LIEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11948991
    Abstract: The present disclosure provides semiconductor structure having an electrical contact. The semiconductor structure includes a semiconductor substrate and a doped polysilicon contact. The doped polysilicon contact is disposed over the semiconductor substrate. The doped polysilicon contact includes a dopant material having a dopant concentration equaling or exceeding about 1015 atom/cm3.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: April 2, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chen-Hao Lien, Cheng-Yan Ji, Chu-Hsiang Hsu
  • Patent number: 11830762
    Abstract: The present disclosure provides a method of manufacturing a semiconductor structure having an electrical contact. The method includes providing a semiconductor substrate; forming a dielectric structure over the semiconductor substrate, the dielectric structure having a trench; filling a polysilicon material in the trench of the dielectric structure; detecting the polysilicon material to determine a region of the polysilicon material having one or more defects formed therein; implanting the polysilicon material with a dopant material into the region; and annealing the polysilicon material to form a doped polysilicon contact.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: November 28, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chen-Hao Lien, Cheng-Yan Ji, Chu-Hsiang Hsu
  • Publication number: 20230187266
    Abstract: The present disclosure provides a method of manufacturing a semiconductor structure having an electrical contact. The method includes providing a semiconductor substrate; forming a dielectric structure over the semiconductor substrate, the dielectric structure having a trench; filling a polysilicon material in the trench of the dielectric structure; detecting the polysilicon material to determine a region of the polysilicon material having one or more defects formed therein; implanting the polysilicon material with a dopant material into the region; and annealing the polysilicon material to form a doped polysilicon contact.
    Type: Application
    Filed: December 9, 2021
    Publication date: June 15, 2023
    Inventors: CHEN-HAO LIEN, CHENG-YAN JI, CHU-HSIANG HSU
  • Publication number: 20230187520
    Abstract: The present disclosure provides semiconductor structure having an electrical contact. The semiconductor structure includes a semiconductor substrate and a doped polysilicon contact. The doped polysilicon contact is disposed over the semiconductor substrate. The doped polysilicon contact includes a dopant material having a dopant concentration equaling or exceeding about 1015 atom/cm3.
    Type: Application
    Filed: December 9, 2021
    Publication date: June 15, 2023
    Inventors: Chen-Hao LIEN, Cheng-Yan JI, Chu-Hsiang HSU
  • Patent number: 11501977
    Abstract: A semiconductor device includes a substrate, a conductive layer, a nitride mask layer, a carbon mask layer and an anti-reflective coating stack. The conductive layer is disposed on the substrate. The nitride mask layer is disposed on the conductive layer, wherein the nitride mask layer has a first stress. The carbon mask layer is disposed on the nitride mask layer, wherein the carbon mask layer has a second stress and a difference between the second stress and the first stress is smaller than 200 MPa. The anti-reflective coating stack is disposed on the carbon mask layer.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: November 15, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chen-Hao Lien
  • Publication number: 20220359221
    Abstract: A semiconductor device includes a substrate, a conductive layer, a nitride mask layer, a carbon mask layer and an anti-reflective coating stack. The conductive layer is disposed on the substrate. The nitride mask layer is disposed on the conductive layer, wherein the nitride mask layer has a first stress. The carbon mask layer is disposed on the nitride mask layer, wherein the carbon mask layer has a second stress and a difference between the second stress and the first stress is smaller than 200 MPa. The anti-reflective coating stack is disposed on the carbon mask layer.
    Type: Application
    Filed: May 10, 2021
    Publication date: November 10, 2022
    Inventor: Chen-Hao LIEN