SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a substrate, a conductive layer, a nitride mask layer, a carbon mask layer and an anti-reflective coating stack. The conductive layer is disposed on the substrate. The nitride mask layer is disposed on the conductive layer, wherein the nitride mask layer has a first stress. The carbon mask layer is disposed on the nitride mask layer, wherein the carbon mask layer has a second stress and a difference between the second stress and the first stress is smaller than 200 MPa. The anti-reflective coating stack is disposed on the carbon mask layer.
The present disclosure relates to a semiconductor device and a manufacturing method thereof. More particularly, the present disclosure relates to a hard mask and a manufacturing method thereof.
Description of Related ArtAs the semiconductor technology has progressed into nanoscale technology, the sizes of the semiconductor devices and the components therein are gradually reduced. In addition, thinner bitlines are desired to connect transistors in the scaled-down semiconductor device. Bitlines are usually produced by etching metal layers to form multiple stripes, and the properties of the hard mask used in the etching process will affect the patterns used for forming bitlines.
SUMMARYIn accordance with some embodiments of the present disclosure, a semiconductor device includes a substrate, a conductive layer, a nitride mask layer, a carbon mask layer and an anti-reflective coating stack. The conductive layer is disposed on the substrate. The nitride mask layer is disposed on the conductive layer, wherein the nitride mask layer has a first stress. The carbon mask layer is disposed on the nitride mask layer, wherein the carbon mask layer has a second stress and a difference between the second stress and the first stress is smaller than 200 MPa. The anti-reflective coating stack is disposed on the carbon mask layer.
In accordance with some embodiments of the present disclosure, the anti-reflective coating stack has a third stress and a difference between the third stress and the second stress is smaller than 300 MPa.
In accordance with some embodiments of the present disclosure, the carbon mask layer includes amorphous carbon.
In accordance with some embodiments of the present disclosure, the carbon mask layer has a first carbon concentration at a top surface of the carbon mask layer and a second carbon concentration at a bottom surface of the carbon mask layer, and the first carbon concentration is greater than the second carbon concentration.
In accordance with some embodiments of the present disclosure, the carbon mask layer has a carbon concentration distribution increasing from the first carbon concentration to a third concentration and then decreasing to the second carbon concentration in a direction from the top surface of the carbon mask layer to the bottom surface of the carbon mask layer.
In accordance with some embodiments of the present disclosure, the carbon mask layer has a thickness in a range of 200 nm to 250 nm.
In accordance with some embodiments of the present disclosure, the conductive layer includes tungsten.
In accordance with some embodiments of the present disclosure, the anti-reflective coating stack includes a first layer made of Si3N4, SiON, or combinations thereof and a second layer made of substantially pure silicon over the first layer.
In accordance with some embodiments of the present disclosure, the semiconductor device further includes a resist disposed on the anti-reflective coating stack.
In accordance with some embodiments of the present disclosure, a method of manufacturing a semiconductor device includes forming a conductive layer on a substrate, forming a nitride mask layer on the conductive layer, forming an amorphous carbon mask layer on the nitride mask layer, performing an implantation process to implant carbon into the amorphous carbon mask layer, forming a dielectric anti-reflective coating layer on the amorphous carbon mask layer, forming a patterned resist on the dielectric anti-reflective coating layer, and etching the dielectric anti-reflective coating layer, the amorphous carbon mask layer, the nitride mask layer and the conductive layer by using the patterned resist as an etch mask to form trenches therein.
In accordance with some embodiments of the present disclosure, the implantation process is performed at a tilt angle with respect to a normal direction of the amorphous carbon mask layer.
In accordance with some embodiments of the present disclosure, the tilt angle is greater than 0° and equal to or less than 50°.
In accordance with some embodiments of the present disclosure, the method further includes determining the tilt angle of the implantation process according to a thickness of the amorphous carbon mask layer.
In accordance with some embodiments of the present disclosure, the method further includes determining an implantation dose of the implantation process according to a thickness of the amorphous carbon mask layer.
In accordance with some embodiments of the present disclosure, the method further includes determining energy of the implantation process according to a thickness of the amorphous carbon mask layer.
In accordance with some embodiments of the present disclosure, the method further includes annealing the amorphous carbon layer after the implantation process and before forming the dielectric anti-reflective coating layer on the amorphous carbon mask layer.
In accordance with some embodiments of the present disclosure, the method further includes annealing the amorphous carbon mask layer after forming the dielectric anti-reflective coating layer on the amorphous carbon mask layer and before forming the patterned resist on the dielectric anti-reflective coating layer.
In accordance with some embodiments of the present disclosure, annealing the amorphous carbon mask layer is performed at the temperature in a range of 900° C. to 1000° C.
In accordance with some embodiments of the present disclosure, the nitride mask layer has a first stress, the implanted carbon mask layer has a second stress, and a difference between the second stress and the first stress is smaller than 200 MPa.
In accordance with some embodiments of the present disclosure, forming the dielectric anti-reflective coating layer includes forming a first layer made of Si3N4, SiON or combinations thereof on the amorphous carbon mask layer and forming a second layer made of silicon on the first layer.
It is to be understood that both the foregoing general description and the following detailed description are by examples, and are intended to provide further explanation of the disclosure as claimed.
The disclosure can be more fully understood by reading the following detailed description of the embodiment, with reference made to the accompanying drawings as follows:
Reference will now be made in detail to the present embodiments of the disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
The present disclosure is related to the formation of a hard mask used to define bitlines in semiconductor devices. In the present disclosure, an amorphous carbon layer implanted with carbon is used to reduce the bitlines bending issue, which can result in straight bitlines and improve the performance of the semiconductor device. The embodiments described below may be used for dynamic random access memory (DRAM), static random access memory (SRAM), flash memory or the like.
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Next, a conductive layer 120 is formed on the substrate 110. The conductive layer 120 will be etched to form bitlines to connect the transistors in the substrate 110 in the subsequent process. In some embodiments, the conductive layer 120 is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atom layer deposition (ALD) or the like. In some embodiments, the conductive layer 120 includes metal and may be tungsten, aluminum, copper, combinations thereof, or the like. In some embodiments, the conductive layer 120 has the thickness in a range of about 25 nm to about 45 nm.
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In some embodiments, the nitride mask layer 130 includes multiple sub-layers. For example, the nitride mask layer 130 includes a first sub-layer 132, a second sub-layer 134 over the first sub-layer 132, and a third sub-layer 136 over the second sub-layer 134. The first sub-layer 132 may be a silicon nitride layer, the second sub-layer 134 may be an oxinitride layer, and the third sub-layer 136 may be a silicon nitride layer. In some embodiments, the first sub-layer 132 has a thickness in a range of about 40 nm to about 60 nm, the second sub-layer 134 has a thickness in a range of about 5 nm to about 10 nm, and the third sub-layer 136 has a thickness in a range of about 90 nm to about 120 nm. In some embodiments, the thickness of the third sub-layer 136 is greater than the thickness of the first sub-layer 132, and/or the thickness of the first sub-layer 132 is greater than the thickness of the second sub-layer 134.
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The implantation process IMP may be performed at different angles based on the thickness of the carbon mask layer 140. In some embodiments, the implantation process IMP is performed in a direction perpendicular to the top surface of the carbon mask layer 140, as shown in
Other parameters, such as implantation dose or implantation energy, of the implantation process IMP may be adjusted based on the thickness D1 of the carbon mask layer 140 and the tilt angle a1. For examples, a greater implantation dose may be used for the carbon mask layer 140 with a greater thickness, and a lower implantation dose may be used for the carbon mask layer 140 with a thinner thickness. In some embodiments, the implantation dose of the implantation process IMP is in a range of about 1×1015 atoms/cm2 to about 9×1015 atoms/cm2. If the implantation process IMP is performed below the disclosed range of the implantation dose, the amount of implanted carbon may be too low to improve properties, such as stress and etching selectivity to the oxide, of the implanted carbon mask layer 140′. If the implantation process IMP is performed above the disclosed range of the implantation dose, the amount of implanted carbon may exceed a saturation concentration, which may not provide a significant improvement of the implanted carbon mask layer 140′.
Further, a greater implantation energy may be used for the carbon mask layer 140 with a greater thickness, and a lower implantation energy may be used for the carbon mask layer 140 with a thinner thickness. In addition, because there is no channeling effect or the channeling effects are reduced, a greater implantation energy may be used for the carbon mask layer 140 at a greater tilt angle a1, and a lower implantation energy may be used for the carbon mask layer 140 at a smaller tilt angle a1. In some embodiments, the implantation energy is in a range of about 20 KeV to about 50 KeV. If the implantation process IMP is performed below the disclosed range of the implantation energy, the implanted carbon may barely reach to a bottom portion of the carbon mask layer 140. If the implantation process IMP is performed above the disclosed range of the implantation energy, the energy may be too strong, so that the implanted carbon may reach the underlying layer (such as the nitride mask layer 130), thereby damaging the underlying layer.
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In some embodiments, the annealing process AN is performed after the formation of the anti-reflective coating stack 150 instead of performed after the formation of the carbon mask layer 140. The annealing process AN performed after the formation of the anti-reflective coating stack 150 may also form a silicon nitride layer on the top surface of the anti-reflective coating stack 150 at the same time. Detailed description of the annealing process AN is similar or the same as details discussed in the
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The present disclosure provides advantages. The bitlines formed by the hard mask in the present disclosure have straight boundaries. With this advantage, the bitlines bending issue is reduced, thereby improving the performance of the semiconductor device.
Although the present disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims.
Claims
1. A semiconductor device, comprising:
- a substrate;
- a conductive layer disposed on the substrate;
- a nitride mask layer disposed on the conductive layer, wherein the nitride mask layer has a first stress;
- a carbon mask layer disposed on the nitride mask layer, wherein the carbon mask layer has a second stress and a difference between the second stress and the first stress is smaller than 200 MPa, and carbon atoms in the carbon mask layer bond to each other with sp3 orbitals; and
- an anti-reflective coating stack disposed on the carbon mask layer.
2. The semiconductor device of claim 1, wherein the anti-reflective coating stack has a third stress and a difference between the third stress and the second stress is smaller than 300 MPa.
3. The semiconductor device of claim 1, wherein the carbon mask layer comprises amorphous carbon.
4. The semiconductor device of claim 3, wherein the carbon mask layer has a first carbon concentration at a top surface of the carbon mask layer and a second carbon concentration at a bottom surface of the carbon mask layer, and the first carbon concentration is greater than the second carbon concentration.
5. The semiconductor device of claim 4, wherein the carbon mask layer has a carbon concentration distribution increasing from the first carbon concentration to a third concentration and then decreasing to the second carbon concentration in a direction from the top surface of the carbon mask layer to the bottom surface of the carbon mask layer.
6. The semiconductor device of claim 3, wherein the carbon mask layer has a thickness in a range of 200 nm to 250 nm.
7. The semiconductor device of claim 1, wherein the conductive layer comprises tungsten.
8. The semiconductor device of claim 1, wherein the anti-reflective coating stack comprises a first layer made of Si3N4, SiON, or combinations thereof and a second layer made of substantially pure silicon over the first layer.
9. The semiconductor device of claim 1, further comprising a resist disposed on the anti-reflective coating stack.
Type: Application
Filed: May 10, 2021
Publication Date: Nov 10, 2022
Inventor: Chen-Hao LIEN (Taipei City)
Application Number: 17/316,697