Patents by Inventor Chen-Hao Po

Chen-Hao Po has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10930746
    Abstract: A differential type non-volatile memory circuit comprising a differential sensing circuit, a differential data line pair, a memory cell array, and a differential bit line pair is provided. The differential sensing circuit has a differential input terminal pair and a differential output terminal pair. The differential data line pair is electrically connected to the differential input terminal pair of the differential sensing circuit. The memory cell array has at least one differential non-volatile memory cell configured to store data. The differential bit line pair is electrically connected between the memory cell array and the differential data line pair. When logic states of the differential output terminal pair start to be different in a read operation phase of the memory cell array, the differential sensing circuit and the differential data line pair are disconnected.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: February 23, 2021
    Assignee: eMemory Technology Inc.
    Inventors: Chen-Hao Po, Cheng-Te Yang
  • Publication number: 20190325924
    Abstract: A differential type non-volatile memory circuit comprising a differential sensing circuit, a differential data line pair, a memory cell array, and a differential bit line pair is provided. The differential sensing circuit has a differential input terminal pair and a differential output terminal pair. The differential data line pair is electrically connected to the differential input terminal pair of the differential sensing circuit. The memory cell array has at least one differential non-volatile memory cell configured to store data. The differential bit line pair is electrically connected between the memory cell array and the differential data line pair. When logic states of the differential output terminal pair start to be different in a read operation phase of the memory cell array, the differential sensing circuit and the differential data line pair are disconnected.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 24, 2019
    Applicant: eMemory Technology Inc.
    Inventors: Chen-Hao Po, Cheng-Te Yang
  • Patent number: 10410691
    Abstract: A non-volatile memory includes a sense amplifier, a switching element and a power switching circuit. A first sub-cell is connected with a word line, a bit line and a source line. A second sub-cell is connected with the word line, an inverted bit line and an inverted source line. During a read cycle, an activation period of the word line contains a first period and a second period. In the first period, the first sub-cell generates a first read current to a first current path, and the second sub-cell generates a second read current to a second current path. The first current path and the second current path are controlled to be opened according to the correlation of the first read current and the second read current.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: September 10, 2019
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventor: Chen-Hao Po
  • Publication number: 20190214059
    Abstract: A non-volatile memory includes a sense amplifier, a switching element and a power switching circuit. A first sub-cell is connected with a word line, a bit line and a source line. A second sub-cell is connected with the word line, an inverted bit line and an inverted source line. During a read cycle, an activation period of the word line contains a first period and a second period. In the first period, the first sub-cell generates a first read current to a first current path, and the second sub-cell generates a second read current to a second current path. The first current path and the second current path are controlled to be opened according to the correlation of the first read current and the second read current.
    Type: Application
    Filed: August 29, 2018
    Publication date: July 11, 2019
    Inventor: Chen-Hao Po
  • Patent number: 10255980
    Abstract: A memory array includes a plurality of memory pages, each memory page includes a plurality of memory cells, and each memory cell includes a floating gate module, a control element, and an erase element. The floating gate module is disposed in a first well, the erase element is disposed in a second well, and the control element is disposed in a third well. The first well, the second well and the third well are disposed in a deep doped region, and memory cells of the plurality of memory pages are all disposed in the deep doped region. Therefore, the spacing rule between deep doped regions is no longer be used to limit the circuit area of the memory array and the circuit area of the memory array can be reduced.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: April 9, 2019
    Assignee: eMemory Technology Inc.
    Inventors: Tsung-Mu Lai, Wen-Hao Ching, Chen-Hao Po
  • Publication number: 20180190357
    Abstract: A memory array includes a plurality of memory pages, each memory page includes a plurality of memory cells, and each memory cell includes a floating gate module, a control element, and an erase element. The floating gate module is disposed in a first well, the erase element is disposed in a second well, and the control element is disposed in a third well. The first well, the second well and the third well are disposed in a deep doped region, and memory cells of the plurality of memory pages are all disposed in the deep doped region. Therefore, the spacing rule between deep doped regions is no longer be used to limit the circuit area of the memory array and the circuit area of the memory array can be reduced.
    Type: Application
    Filed: February 26, 2018
    Publication date: July 5, 2018
    Inventors: Tsung-Mu Lai, Wen-Hao Ching, Chen-Hao Po
  • Patent number: 9941011
    Abstract: A memory array includes a plurality of memory pages, each memory page includes a plurality of memory cells, and each memory cell includes a floating gate module, a control element, and an erase element. The floating gate module is disposed in a first well, the erase element is disposed in a second well, and the control element is disposed in a third well. The first well, the second well and the third well are disposed in a deep doped region, and memory cells of the plurality of memory pages are all disposed in the deep doped region. Therefore, the spacing rule between deep doped regions is no longer be used to limit the circuit area of the memory array and the circuit area of the memory array can be reduced.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: April 10, 2018
    Assignee: eMemory Technology Inc.
    Inventors: Tsung-Mu Lai, Wen-Hao Ching, Chen-Hao Po
  • Patent number: 9882566
    Abstract: A driving circuit includes a first driver, a switching circuit and a second driver. The first driver receives an input signal and an inverted input signal, and generates a driving signal. The switching circuit receives the driving signal and a first mode signal. Moreover, an output signal is outputted from an output terminal. The second driver is connected with the output terminal.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: January 30, 2018
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Chen-Hao Po, Wu-Chang Chang
  • Patent number: 9847133
    Abstract: A memory array includes a plurality of memory pages, each memory page includes a plurality of memory bytes, each memory byte includes a plurality of memory cells, and each memory cell includes a floating gate module, a control element, and an erase element. Memory bytes of the same column are coupled to the same erase line, and memory bytes of different columns are coupled to different erase lines. Therefore, the memory array is able to support byte operations while the memory cells of the same memory byte can share the same wells. The circuit area of the memory array can be reduced and the operation of the memory array can be more flexible.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: December 19, 2017
    Assignee: eMemory Technology Inc.
    Inventors: Tsung-Mu Lai, Chih-Hsin Chen, Shih-Chen Wang, Chen-Hao Po
  • Patent number: 9786340
    Abstract: A driving circuit includes a driving stage with a first level shifter and a second level shifter. The first level shifter includes an input terminal receiving a first control signal, an inverted input terminal receiving an inverted first control signal, a first output terminal, and a second output terminal. The second level shifter includes an input terminal receiving a second control signal, an inverted input terminal receiving an inverted second control signal, a third output terminal, and a fourth output terminal. The first output terminal and the third output terminal are connected with each other to generate an output signal. The second output terminal and the fourth output terminal are connected with each other to generate an inverted output signal. Moreover, one of the first level shifter and the second level shifter is enabled according to an operation mode of the driving circuit.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: October 10, 2017
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventor: Chen-Hao Po
  • Publication number: 20170206970
    Abstract: A memory array includes a plurality of memory pages, each memory page includes a plurality of memory bytes, each memory byte includes a plurality of memory cells, and each memory cell includes a floating gate module, a control element, and an erase element. Memory bytes of the same column are coupled to the same erase line, and memory bytes of different columns are coupled to different erase lines. Therefore, the memory array is able to support byte operations while the memory cells of the same memory byte can share the same wells. The circuit area of the memory array can be reduced and the operation of the memory array can be more flexible.
    Type: Application
    Filed: May 10, 2016
    Publication date: July 20, 2017
    Inventors: Tsung-Mu Lai, Chih-Hsin Chen, Shih-Chen Wang, Chen-Hao Po
  • Publication number: 20170206968
    Abstract: A memory array includes a plurality of memory pages, each memory page includes a plurality of memory cells, and each memory cell includes a floating gate module, a control element, and an erase element. The floating gate module is disposed in a first well, the erase element is disposed in a second well, and the control element is disposed in a third well. The first well, the second well and the third well are disposed in a deep doped region, and memory cells of the plurality of memory pages are all disposed in the deep doped region. Therefore, the spacing rule between deep doped regions is no longer be used to limit the circuit area of the memory array and the circuit area of the memory array can be reduced.
    Type: Application
    Filed: November 16, 2016
    Publication date: July 20, 2017
    Inventors: Tsung-Mu Lai, Wen-Hao Ching, Chen-Hao Po
  • Publication number: 20170206941
    Abstract: A driving circuit includes a driving stage with a first level shifter and a second level shifter. The first level shifter includes an input terminal receiving a first control signal, an inverted input terminal receiving an inverted first control signal, a first output terminal, and a second output terminal. The second level shifter includes an input terminal receiving a second control signal, an inverted input terminal receiving an inverted second control signal, a third output terminal, and a fourth output terminal. The first output terminal and the third output terminal are connected with each other to generate an output signal. The second output terminal and the fourth output terminal are connected with each other to generate an inverted output signal. Moreover, one of the first level shifter and the second level shifter is enabled according to an operation mode of the driving circuit.
    Type: Application
    Filed: November 9, 2016
    Publication date: July 20, 2017
    Inventor: Chen-Hao Po
  • Patent number: 9633734
    Abstract: A driving circuit includes a first driver, a switching circuit and a second driver. The first driver receives and input signal and an inverted input signal, and generates a driving signal. The switching circuit receives the driving signal and a first mode signal. Moreover, an output signal is outputted from an output terminal. The second driver is connected with the output terminal.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: April 25, 2017
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventor: Chen-Hao Po
  • Patent number: 9520196
    Abstract: A voltage switch circuit is connected to a memory cell of a non-volatile memory. When the non-volatile memory is in a program mode and the memory cell is a selected memory cell, two output terminals provide a high voltage. When the non-volatile memory is in the program mode and the memory cell is a non-selected memory cell, the two output terminals provide a medium voltage and a ground voltage. When the non-volatile memory is in an erase mode and the memory cell is the selected memory cell, the two output terminals provide the high voltage and the ground voltage. When the non-volatile memory is in the erase mode and the memory cell is the non-selected memory cell, the two output terminals provide the ground voltage. When the non-volatile memory is in a read mode, the two output terminals provide a read voltage.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: December 13, 2016
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventor: Chen-Hao Po
  • Publication number: 20160005487
    Abstract: A voltage switch circuit includes plural transistors, a first control circuit and a second control circuit. The first transistor has a source terminal connected to a first voltage source and a gate terminal connected to a node b1. The second transistor has a source terminal connected to a drain terminal of the first transistor, a gate terminal receiving an enabling signal and a drain terminal connected to a node b2. The third transistor has a source terminal connected to the node b2, a gate terminal connected to a second voltage source and a drain terminal connected to an output terminal. The first control circuit is connected to the node b1. The second control circuit is connected to the output terminal.
    Type: Application
    Filed: October 30, 2014
    Publication date: January 7, 2016
    Inventor: Chen-Hao Po
  • Patent number: 9224490
    Abstract: A voltage switch circuit includes plural transistors, a first control circuit and a second control circuit. The first transistor has a source terminal connected to a first voltage source and a gate terminal connected to a node b1. The second transistor has a source terminal connected to a drain terminal of the first transistor, a gate terminal receiving an enabling signal and a drain terminal connected to a node b2. The third transistor has a source terminal connected to the node b2, a gate terminal connected to a second voltage source and a drain terminal connected to an output terminal. The first control circuit is connected to the node b1. The second control circuit is connected to the output terminal.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: December 29, 2015
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventor: Chen-Hao Po
  • Patent number: 9190415
    Abstract: A voltage switch circuit includes four transistors. The four transistors may be transistors used to build logic gates. The operation of the voltage switch circuit may include precharging the output terminal of the voltage switch circuit, conditioning of the voltage switch circuit and boosting the voltage of the output terminal.
    Type: Grant
    Filed: June 29, 2014
    Date of Patent: November 17, 2015
    Assignee: eMemory Technology Inc.
    Inventor: Chen-Hao Po
  • Patent number: 9019780
    Abstract: A non-volatile memory apparatus and a data verification method thereof are provided. The non-volatile memory apparatus includes a plurality of memory cells, a page buffer, a write circuit, a sense amplifier, and a sense and compare circuit. The page buffer stores a plurality of buffered data and programs the plurality of memory cells according to the plurality of buffered data. The write circuit receives a program data or a rewrite-in data and writes the program data or the rewrite-in data to the page buffer. The sense amplifier senses data read from the memory cells for generating a read-out data. The sense and compare circuit reads the buffered data, and compares the read-out data and a compared buffered data to generate a rewrite-in data. The sense and compare circuit determines the rewrite-in data to be the buffered data or an inhibiting data according to the compared result.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: April 28, 2015
    Assignee: eMemory Technology Inc.
    Inventors: Yih-Lang Lin, Chen-Hao Po
  • Publication number: 20150098278
    Abstract: A non-volatile memory apparatus and a data verification method thereof are provided. The non-volatile memory apparatus includes a plurality of memory cells, a page buffer, a write circuit, a sense amplifier, and a sense and compare circuit. The page buffer stores a plurality of buffered data and programs the plurality of memory cells according to the plurality of buffered data. The write circuit receives a program data or a rewrite-in data and writes the program data or the rewrite-in data to the page buffer. The sense amplifier senses data read from the memory cells for generating a read-out data. The sense and compare circuit reads the buffered data, and compares the read-out data and a compared buffered data to generate a rewrite-in data. The sense and compare circuit determines the rewrite-in data to be the buffered data or an inhibiting data according to the compared result.
    Type: Application
    Filed: October 8, 2013
    Publication date: April 9, 2015
    Applicant: eMemory Technology Inc.
    Inventors: Yih-Lang Lin, Chen-Hao Po