Patents by Inventor Chen-Hao Po
Chen-Hao Po has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150098278Abstract: A non-volatile memory apparatus and a data verification method thereof are provided. The non-volatile memory apparatus includes a plurality of memory cells, a page buffer, a write circuit, a sense amplifier, and a sense and compare circuit. The page buffer stores a plurality of buffered data and programs the plurality of memory cells according to the plurality of buffered data. The write circuit receives a program data or a rewrite-in data and writes the program data or the rewrite-in data to the page buffer. The sense amplifier senses data read from the memory cells for generating a read-out data. The sense and compare circuit reads the buffered data, and compares the read-out data and a compared buffered data to generate a rewrite-in data. The sense and compare circuit determines the rewrite-in data to be the buffered data or an inhibiting data according to the compared result.Type: ApplicationFiled: October 8, 2013Publication date: April 9, 2015Applicant: eMemory Technology Inc.Inventors: Yih-Lang Lin, Chen-Hao Po
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Publication number: 20150092507Abstract: A voltage switch circuit includes four transistors. The four transistors may be transistors used to build logic gates. The operation of the voltage switch circuit may include precharging the output terminal of the voltage switch circuit, conditioning of the voltage switch circuit and boosting the voltage of the output terminal.Type: ApplicationFiled: June 29, 2014Publication date: April 2, 2015Inventor: Chen-Hao Po
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Patent number: 8841942Abstract: A voltage switch circuit uses PMOS transistors to withstand high voltage stress. Consequently, the NMOS transistors are not subject to high voltage stress. The lightly-doped PMOS transistors are compatible with a logic circuit manufacturing process. Consequently, the voltage switch circuit may be produced by a logic circuit manufacturing process.Type: GrantFiled: December 19, 2013Date of Patent: September 23, 2014Assignee: eMemory Technology Inc.Inventors: Chen-Hao Po, Chiun-Chi Shen
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Publication number: 20140177350Abstract: A single-ended sense amplifier and a method for reading a memory cell are disclosed. The method includes the following steps. A bit line is charged according to a control signal. Thereafter, whether the dropoff time of the bit line voltage is greater or less than a predetermined time is deteremined. When the dropoff time of the voltage of the bit line is less than the predetermined time period, a first operation is sensed. On the other hand, when the dropoff time of the voltage of the bit line is greater than the predetermined time period, a second operation is sensed. The dropoff time of the voltage of the bit line is determined according to a parasitic capacitance on the bit line. A logic level of a sensing transistor circuit is retained and an output data signal according to the operation sensed is generated.Type: ApplicationFiled: December 23, 2012Publication date: June 26, 2014Applicant: EMEMORY TECHNOLOGY INC.Inventors: Yung-Jui Chen, Chen-Hao Po, Chih-Hao Huang
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Publication number: 20140103988Abstract: A voltage switch circuit uses PMOS transistors to withstand high voltage stress. Consequently, the NMOS transistors are not subject to high voltage stress. The lightly-doped PMOS transistors are compatible with a logic circuit manufacturing process. Consequently, the voltage switch circuit may be produced by a logic circuit manufacturing process.Type: ApplicationFiled: December 19, 2013Publication date: April 17, 2014Applicant: EMEMORY TECHNOLOGY INC.Inventors: Chen-Hao Po, Chiun-Chi Shen
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Patent number: 8653878Abstract: A voltage switch circuit uses PMOS transistors to withstand high voltage stress. Consequently, the NMOS transistors are not subject to high voltage stress. The lightly-doped PMOS transistors are compatible with a logic circuit manufacturing process. Consequently, the voltage switch circuit may be produced by a logic circuit manufacturing process.Type: GrantFiled: March 19, 2012Date of Patent: February 18, 2014Assignee: Ememory Technology Inc.Inventors: Chen-Hao Po, Chiun-Chi Shen
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Publication number: 20130099850Abstract: A voltage switch circuit uses PMOS transistors to withstand high voltage stress. Consequently, the NMOS transistors are not subject to high voltage stress. The lightly-doped PMOS transistors are compatible with a logic circuit manufacturing process. Consequently, the voltage switch circuit may be produced by a logic circuit manufacturing process.Type: ApplicationFiled: March 19, 2012Publication date: April 25, 2013Applicant: eMemory Technology Inc.Inventors: Chen-Hao Po, Chiun-Chi Shen
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Patent number: 8373485Abstract: A voltage level shifting apparatus is disclosed. The voltage level shifting apparatus has a cross-coupled transistor pair, a plurality of transistor pairs, a first diode string, a second diode string and an input transistor pair. One of the transistor pairs is coupled to the cross-coupled transistor pair, and the transistor pairs are controlled by a plurality of reference voltages. The first and the second diode strings are coupled between two of the transistor pairs. Each of the first and the second diode strings has at least one diode. The input transistor pair receives a first and a second input voltage, and the first and second input voltages are complementary signals. The cross-coupled transistor pair generates and outputs a first output voltage and a second output voltage by shifting the voltage level of the first and the second input voltage.Type: GrantFiled: April 20, 2011Date of Patent: February 12, 2013Assignee: eMemory Technology Inc.Inventors: Chen-Hao Po, Yen-Tai Lin, Way-Chen Wu, Ching-Shan Chien
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Publication number: 20120268188Abstract: A voltage level shifting apparatus is disclosed. The voltage level shifting apparatus has a cross-coupled transistor pair, a plurality of transistor pairs, a first diode string, a second diode string and an input transistor pair. One of the transistor pairs is coupled to the cross-coupled transistor pair, and the transistor pairs are controlled by a plurality of reference voltages. The first and the second diode strings are coupled between two of the transistor pairs. Each of the first and the second diode strings has at least one diode. The input transistor pair receives a first and a second input voltage, and the first and second input voltages are complementary signals. The cross-coupled transistor pair generates and outputs a first output voltage and a second output voltage by shifting the voltage level of the first and the second input voltage.Type: ApplicationFiled: April 20, 2011Publication date: October 25, 2012Applicant: EMEMORY TECHNOLOGY INC.Inventors: Chen-Hao Po, Yen-Tai Lin, Way-Chen Wu, Ching-Shan Chien
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Publication number: 20110194355Abstract: A verify while write (VWW) scheme for a non-volatile memory (NVM) cell is provided. The VWW scheme conducts simultaneous write and verify operation by sensing the memory cell current during the write pulse at exactly the same write bias condition in contrast to the “verify+retry-write” write algorithm in the prior art. The VWW scheme removes the iterative “verify and then retry-write” to save both control timing and power consumed in these iterations. Instead, the VWW scheme is composed of single write pulse only in the entire algorithm with exact write pulse width trimmed automatically for multiple memory cells undergoing parallel writing within one write command assertion. Faster write speed, more power efficient write operation and higher reliability of non-volatile semiconductor memory cell are thus achieved with the VWW scheme in this present disclosure.Type: ApplicationFiled: February 8, 2010Publication date: August 11, 2011Applicant: eMemory Technology Inc.Inventor: Chen-Hao Po
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Patent number: 7889541Abstract: A SRAM cell structure includes a first N type switch, a second N type switch, a first storage node, and a second storage node. The first N type switch has a control terminal connected to a word line and a first terminal connected to a bit line. The second N type switch has a control terminal connected to the word line and a first terminal connected to an inverted bit line. The first storage node has a first terminal connected to a second terminal of the first N type switch. The second storage node has a first terminal connected to a second terminal of the second N type switch.Type: GrantFiled: April 10, 2009Date of Patent: February 15, 2011Assignee: Faraday Technology Corp.Inventors: Wei-Chiang Shih, Chen-Hao Po, Kwo-Jen Liu
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Publication number: 20090257273Abstract: A SRAM cell structure includes a first N type switch, a second N type switch, a first storage node, and a second storage node. The first N type switch has a control terminal connected to a word line and a first terminal connected to a bit line. The second N type switch has a control terminal connected to the word line and a first terminal connected to an inverted bit line. The first storage node has a first terminal connected to a second terminal of the first N type switch. The second storage node has a first terminal connected to a second terminal of the second N type switch.Type: ApplicationFiled: April 10, 2009Publication date: October 15, 2009Applicant: FARADAY TECHNOLOGY CORPORATIONInventors: WEI-CHIANG SHIH, CHEN-HAO PO, KWO-JEN LIU
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Patent number: 7397717Abstract: A serial peripheral flash memory device uses a plurality of dummy input/output terminals to enable the selection of a parallel mode for devices that have a slower serial clock speed. In parallel mode, data is transmitted over the plurality of dummy input/output terminals to allow a plurality of bits to be transmitted at the same time improving the data transmission rate at the slower serial clock speed.Type: GrantFiled: May 26, 2005Date of Patent: July 8, 2008Assignee: Macronix International Co., Ltd.Inventors: Han-Sung Chen, Chia-Yen Yeh, Chen-Hao Po, Ching-Chung Lin
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Publication number: 20060268642Abstract: A serial peripheral flash memory device uses a plurality of dummy input/output terminals to enable the selection of a parallel mode for devices that have a slower serial clock speed. In parallel mode, data is transmitted over the plurality of dummy input/output terminals to allow a plurality of bits to be transmitted at the same time improving the data transmission rate at the slower serial clock speed.Type: ApplicationFiled: May 26, 2005Publication date: November 30, 2006Inventors: Han-Sung Chen, Chia-Yen Yeh, Chen-Hao Po, Ching-Chung Lin
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Patent number: 6795350Abstract: A circuit and method for tuning a reference bit line loading to a sense amplifier that compares the voltage on a sense node with the voltage on a reference data line node to determine a sensing signal on the output of the sense amplifier. The sense node is selectively connected to a memory cell to generate the sensed voltage on the sense node to represent the data stored in the selected memory cell. There is included a reference cell unit and a reference bit line unit connected to the reference data line node. The reference cell unit contains at least one reference cell to provide a reference current to the reference bit line node, and the reference bit line unit contains at least one reference bit line optionally cut to determine the reference bit line loading.Type: GrantFiled: January 27, 2003Date of Patent: September 21, 2004Assignee: Macronix International Co., Ltd.Inventors: Han-Sung Chen, Kuo-Yu Liao, Chen-Hao Po, Chun-Hsiung Hung
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Publication number: 20040008546Abstract: A circuit and method for tuning a reference bit line loading to a sense amplifier that compares the voltage on a sense node with the voltage on a reference data line node to determine a sensing signal on the output of the sense amplifier. The sense node is selectively connected to a memory cell to generate the sensed voltage on the sense node to represent the data stored in the selected memory cell. There is included a reference cell unit and a reference bit line unit connected to the reference data line node. The reference cell unit contains at least one reference cell to provide a reference current to the reference bit line node, and the reference bit line unit contains at least one reference bit line optionally cut to determine the reference bit line loading.Type: ApplicationFiled: January 27, 2003Publication date: January 15, 2004Inventors: Han-Sung Chen, Kuo-Yu Liao, Chen-Hao Po, Chun-Hsiung Hung