Patents by Inventor Chen Hsieh

Chen Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145372
    Abstract: A substrate structure is provided, in which an insulating protection layer is formed on a substrate body having a plurality of electrical contact pads, and the insulating protection layer has a plurality of openings corresponding to the plurality of exposed electrical contact pads, and the insulating protection layer is formed with a hollow portion surrounding a partial edge of at least one of the electrical contact pads at at least one of the openings, so as to reduce the barrier of the insulating protection layer.
    Type: Application
    Filed: December 22, 2022
    Publication date: May 2, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chia-Wen TSAO, Wen-Chen HSIEH, Yi-Lin TSAI, Hsiu-Fang CHIEN
  • Publication number: 20240142544
    Abstract: A testing system includes: a dividing circuit configured to receive a testing signal and provide a plurality of input signals according to the testing signal; and a plurality of integrated power-amplifiers coupled to the dividing circuit, each of the plurality of integrated power-amplifiers being configured to be tested by receiving a respective input signal of the plurality of input signals and generating a respective output signal for a predetermined testing time.
    Type: Application
    Filed: January 11, 2024
    Publication date: May 2, 2024
    Inventors: HSIEH-HUNG HSIEH, WU-CHEN LIN, YEN-JEN CHEN, TZU-JIN YEH
  • Patent number: 11967613
    Abstract: A semiconductor structure includes a substrate, and an active device and a passive device over the substrate. The active device is disposed in a first region of the substrate, and the passive device is disposed in a second region of the substrate. The semiconductor structure further includes a shielding structure and a passivation layer. The shielding structure includes a barrier layer and a ceiling layer. The barrier layer is on the passive device and the active device, and the ceiling layer is on the barrier layer. The passivation layer is under the barrier layer and covers a top surface of the passive device. An air cavity is defined by sidewalls of the barrier layer, a bottom surface of the ceiling layer, and the substrate.
    Type: Grant
    Filed: May 16, 2023
    Date of Patent: April 23, 2024
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Ju-Hsien Lin, Jung-Tao Chung, Shu-Hsiao Tsai, Hsi-Tsung Lin, Chen-An Hsieh, Yi-Han Chen, Yao-Ting Shao
  • Publication number: 20240124163
    Abstract: A magnetic multi-pole propulsion array system is applied to at least one external cathode and includes a plurality of magnetic multi-pole thrusters connected adjacent to each other. Each magnetic multi-pole thruster includes a propellant provider, a discharge chamber, an anode and a plurality of magnetic components. The propellant provider outputs propellant. The discharge chamber is connected with the propellant provider to accommodate the propellant. The anode is disposed inside the discharge chamber to generate an electric field. The plurality of magnetic components is respectively disposed on several sides of the discharge chamber. One of the several sides of the discharge chamber of the magnetic multi-pole thruster is applied for one side of a discharge chamber of another magnetic multi-pole thruster.
    Type: Application
    Filed: December 19, 2022
    Publication date: April 18, 2024
    Applicant: National Cheng Kung University
    Inventors: Yueh-Heng Li, Yu-Ting Wu, Chao-Wei Huang, Wei-Cheng Lo, Hsun-Chen Hsieh, Ping-Han Huang, Yi-Long Huang, Sheng-Wen Liu, Wei-Cheng Lien
  • Publication number: 20240128009
    Abstract: A magnetic device includes a magnetic core and at least two windings. The magnetic core includes an annular main body and a hollow portion. Each of the at least two windings includes a coil with a plurality of turns. Each turn of the coil penetrates through the hollow portion and is disposed around the annular main body. The at least two windings are disposed around the annular main body to form at least three winding regions. Each of the winding regions except a winding region which is last formed has at least three winding layers stacked up one by one. The number of the winding layers of the winding regions except the winding region which is last formed is odd and greater than or equal to three.
    Type: Application
    Filed: January 12, 2023
    Publication date: April 18, 2024
    Inventors: Meng-Chen Hsieh, Chun-Ching Yen, Huai-Pei Tung
  • Patent number: 11959137
    Abstract: Disclosed herein, inter alia, are compounds, compositions, and methods of use thereof in the sequencing of a nucleic acid.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: April 16, 2024
    Assignee: THE TRUSTEES OF COLUMBIA UNIVERSITY IN THE CITY OF NEW YORK
    Inventors: Jingyue Ju, Xiaoxu Li, Xin Chen, Zengmin Li, Shiv Kumar, Shundi Shi, Cheng Guo, Jianyi Ren, Min-Kang Hsieh, Minchen Chien, Chuanjuan Tao, Ece Erturk, Sergey Kalachikov, James J. Russo
  • Publication number: 20240120236
    Abstract: A method includes etching a gate stack in a wafer to form a trench, depositing a silicon nitride liner extending into the trench, and depositing a silicon oxide layer. The process of depositing the silicon oxide layer includes performing a treatment process on the wafer using a process gas including nitrogen and hydrogen, and performing a soaking process on the wafer using a silicon precursor.
    Type: Application
    Filed: April 25, 2023
    Publication date: April 11, 2024
    Inventors: Tai-Jung Kuo, Po-Cheng Shih, Wan Chen Hsieh, Zhen-Cheng Wu, Chia-Hui Lin, Tze-Liang Lee
  • Publication number: 20240087879
    Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.
    Type: Application
    Filed: November 14, 2023
    Publication date: March 14, 2024
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Hsun-Chung Kuang, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 11913980
    Abstract: A power detection circuit is provided. The power detection circuit includes a comparator circuit operative to generate an output signal in response to an input signal. The output signal is configured to change from a first value to a second value in response to the input signal attaining a first threshold value. The output signal is configured to change from the second value to the first value in response to the input signal subsequently attaining a second threshold value. A current limiting circuit is connected to the comparator circuit and operative to limit a leakage current of the comparator circuit.
    Type: Grant
    Filed: March 6, 2023
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chen Kuo, Chiting Cheng, Wei-jer Hsieh, Yangsyu Lin
  • Patent number: 11893229
    Abstract: A portable electronic device and a one-hand touch operation method thereof are provided. A touch operation performed on a touch screen is detected. When a shift amount of the touch operation in a first direction is greater than a first threshold, whether to activate a one-hand mode is determined according to a shift amount of the touch operation in a second direction. When the one-hand mode is activated, the operation interface image is zoomed out or shifted, and displayed in a one-hand mode interface display region.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: February 6, 2024
    Assignee: ASUSTeK COMPUTER INC.
    Inventors: Meng Chen Hsieh, Chen-Yu Hsu, Chih-Hsien Yang, I-Hsi Wu, Hsin-Yi Pu
  • Publication number: 20240034560
    Abstract: Disclosed is an Object Recognition Warehousing Method for STORE or FETCH an object through a pretrained Object Recognition Model (ORM). Image of an object is taken by an image sensor for Object Recognition, and system automatically provides options of classification and labelling A physical object without package is recognized for STORE according to the present invention.
    Type: Application
    Filed: July 26, 2022
    Publication date: February 1, 2024
    Inventor: Yu-Chen HSIEH
  • Patent number: 11859599
    Abstract: A vacuum arc thruster with multi-layer insulation includes a housing, an anode unit and a cathode unit spaced apart from each other in the housing, and an insulator disposed between the anode unit and the cathode unit. The insulator includes a plurality of fuel layers and a plurality of insulating layers. Each insulating layer is located between every two adjacent fuel layers. Accordingly, a multiple-layer design is formed by arranging the fuel layers and the insulating layers which are made of different materials in an alternating manner, thereby attaining the maximum field emission effect, increasing the stability and efficacy of operating the vacuum arc thruster, and prolonging the service life of the thruster.
    Type: Grant
    Filed: June 27, 2023
    Date of Patent: January 2, 2024
    Assignee: National Cheng Kung University
    Inventors: Yueh-Heng Li, Hsun-Chen Hsieh, Ping-Han Huang, Wei-Cheng Lo
  • Publication number: 20230389492
    Abstract: The present invention generally relates to a hydroponic culture medium and a hydroponic planting system, more particularly to a Houttuynia cordata hydroponic culture medium, a Houttuynia cordata hydroponic planting system, Houttuynia cordata extracts, a method, and applications thereof.
    Type: Application
    Filed: March 14, 2023
    Publication date: December 7, 2023
    Inventors: FANG-RONG CHANG, WEI-HUNG WU, YI-HONG TSAI, CHUNG-HSIEN CHEN, YEN-CHI LOO, HSUEH-ER CHEN, YEN-CHANG CHEN, HUI-PING HSIEH, CHEN HSIEH
  • Publication number: 20230352442
    Abstract: A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region.
    Type: Application
    Filed: July 10, 2023
    Publication date: November 2, 2023
    Inventors: Hui-Jung Tsai, Yun Chen Hsieh, Jyun-Siang Peng, Tai Min Chang, Yi-Yang Lei, Hung-Jui Kuo, Chen-Hua Yu
  • Publication number: 20230343692
    Abstract: An electronic package is provided and includes a substrate structure, an electronic element disposed on the substrate structure and an encapsulation layer encapsulating the electronic element, where at least one functional circuit is formed on a surface of a substrate body of the substrate structure, and a wire having a smaller width is arranged on a boundary line at a junction between an encapsulation area and a peripheral area, so that when a mold for forming the encapsulation layer is formed to cover the substrate structure, the mold will create a gap around the wire to serve as an exhaust passage. Therefore, when the encapsulation layer is formed, the exhaust passage can be used to exhaust air, so as to avoid problems such as the occurrence of voids or overflows of the encapsulation layer.
    Type: Application
    Filed: July 7, 2022
    Publication date: October 26, 2023
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Wen-Chen Hsieh, Ya-Ting Chi, Chia-Wen Tsao, Hsin-Yin Chang, Yi-Lin Tsai, Hsiu-Fang Chien
  • Publication number: 20230335406
    Abstract: A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.
    Type: Application
    Filed: June 26, 2023
    Publication date: October 19, 2023
    Inventors: Wen-Ju Chen, Chung-Ting Ko, Wan-Chen Hsieh, Chun-Ming Lung, Tai-Chun Huang, Chi On Chui
  • Publication number: 20230282697
    Abstract: A semiconductor structure includes a substrate, and an active device and a passive device over the substrate. The active device is disposed in a first region of the substrate, and the passive device is disposed in a second region of the substrate. The semiconductor structure further includes a shielding structure and a passivation layer. The shielding structure includes a barrier layer and a ceiling layer. The barrier layer is on the passive device and the active device, and the ceiling layer is on the barrier layer. The passivation layer is under the barrier layer and covers a top surface of the passive device. An air cavity is defined by sidewalls of the barrier layer, a bottom surface of the ceiling layer, and the substrate.
    Type: Application
    Filed: May 16, 2023
    Publication date: September 7, 2023
    Inventors: Ju-Hsien LIN, Jung-Tao CHUNG, Shu-Hsiao TSAI, Hsi-Tsung LIN, Chen-An HSIEH, Yi-Han CHEN, Yao-Ting SHAO
  • Publication number: 20230274976
    Abstract: A method includes forming a metal seed layer on a dielectric layer, and forming a patterned mask over the metal seed layer. An opening in the patterned mask is over a first portion of the dielectric layer, and the patterned mask overlaps a second portion of the dielectric layer. The method further includes plating a metal region in the opening, removing the patterned mask to expose portions of the metal seed layer, etching the exposed portions of the metal seed layer, performing a plasma treatment on a surface of the second portion of the dielectric layer, and performing an etching process on the surface of the second portion of the dielectric layer.
    Type: Application
    Filed: April 18, 2023
    Publication date: August 31, 2023
    Inventors: Yun Chen Hsieh, Hui-Jung Tsai, Hung-Jui Kuo, Chen-Hua Yu
  • Patent number: 11742317
    Abstract: A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: August 29, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hui-Jung Tsai, Yun Chen Hsieh, Jyun-Siang Peng, Tai-Min Chang, Yi-Yang Lei, Hung-Jui Kuo, Chen-Hua Yu
  • Patent number: D1019928
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: March 26, 2024
    Assignee: HOTECK INC.
    Inventors: Lung-Fa Hsieh, Yu-Chen Hsieh