Abstract: An electronic device for assisting driver in recording images is introduced. In the electronic device, a panoramic camera unit is installed on a transportation vehicle to capture an initial video. A positioning unit detects a real-time location of the transportation vehicle. A database stores scenic spot information including multiple scenic spot locations. An intelligence processing unit receives the initial video and uses artificial intelligence to identify a user's image and an image of the scenic spot to be locked at the scenic spot location. The intelligence processing unit receives the real-time location and determines the direction of travel. The intelligence processing unit reads the scenic spot information and determines a viewing range of the transportation vehicle entering the scenic spot location based on the real-time location and the direction of travel to capture a time period within the viewing range from the initial video and crop a recorded video.

Abstract: The present invention provides an enzyme composition and a preparation method therefor and a use thereof. The enzyme composition includes an enzyme, an enzyme stabilizer, a filler, and a primer designed for a target nucleic acid. The enzyme composition can be preserved at room temperature and maintain good stability and activity, thereby improving adaptability of the enzyme composition to an ambient temperature. In addition, the enzyme is integrated with the primer, so that the enzyme composition is used in PCR detection, especially in LAMP nucleic acid amplification, a time for preparing a reaction system is shortened, and an operation procedure is simplified. Therefore, the enzyme composition is suitable for large-scale production. The enzyme composition is applied to target nucleic acid detection to maintain high sensitivity and detection stability.

Abstract: A polymer composite for preparing a low dielectric resin composition having a dielectric loss tangent (Df) that is less than or equal to 0.00200 is provided. The polymer composite includes a first styrene-based copolymer having a weight average molecular weight that is lower than 20,000 g/mol and a second styrene-based copolymer having a weight average molecular weight that is higher than 20,000 g/mol, wherein the weight ratio of the first styrene-based copolymer to the second styrene-based copolymer is from 5/95 to 95/5.

Abstract: Various embodiments of the present application are directed towards an integrated chip (IC). The IC comprises a trench capacitor overlying a substrate. The trench capacitor comprises a plurality of capacitor electrode structures, a plurality of warping reduction structures, and a plurality of capacitor dielectric structures. The plurality of capacitor electrode structures, the plurality of warping reduction structures, and the plurality of capacitor dielectric structures are alternatingly stacked and define a trench segment that extends vertically into the substrate. The plurality of capacitor electrode structures comprise a metal component and a nitrogen component. The plurality of warping reduction structures comprise the metal component, the nitrogen component, and an oxygen component.

Abstract: A device for assessing early dementia by testing gripping strength comprises a main member, a sensing member, and a control system. The main member has a display portion and a gripping portion. The sensing member is connected to the gripping portion to be pressed by a subject to generate a sensing signal. The control system is provided in the main member and having a control unit, a timer, a grip sensing module, and a determining module. The timer records a pressing time of the subject. The grip sensing module receives the sensing signal from the sensing members and generates a gripping strength signal according to the sensing signals. The determining module receives the pressing time and the gripping strength signal, and generates an assessing result by comparing the gripping strength signal with a gripping strength threshold and comparing the pressing time with a time threshold.

Abstract: A hydrocarbon resin polymer including a repeating unit (A) is derived from dicyclopentadiene (DCPD). The hydrocarbon resin polymer has a fluorine substituent, and the content of the fluorine substituent is 100 to 4500 ppm based on the total weight of the hydrocarbon resin polymer. A manufacturing method of the above hydrocarbon resin polymer. The manufacturing method includes polymerizing a mixture in the presence of a fluorine-containing compound, wherein the fluorine-containing compound is a boron trifluoride complex and the mixture includes a dicyclopentadiene. A substrate structure includes a resin layer, and a conductive layer disposed on the resin layer. The resin layer is formed from a resin composition including the above hydrocarbon resin polymer using a cross-linking process.

Abstract: Low-flow tungsten chemical vapor deposition (CVD) techniques described herein provide substantially uniform deposition of tungsten on a semiconductor substrate. In some implementations, a flow of a processing vapor is provided to a CVD processing chamber such that a flow rate of tungsten hexafluoride in the processing vapor results in the tungsten layer being grown at a slower rate than a higher flow rate of the tungsten hexafluoride to promote substantially uniform growth of the tungsten layer. In this way, the low-flow tungsten CVD techniques may be used to achieve similar surface uniformity performance to an atomic layer deposition (ALD) while being a faster deposition process relative to ALD (e.g., due to the lower deposition rate and large quantity of alternating processing cycles of ALD). This reduces the likelihood of defect formation in the tungsten layer while increasing the throughput of semiconductor device processing for the semiconductor substrate (and other semiconductor substrates).

Abstract: A semiconductor package includes a circuit substrate, a die, a frame structure, and a heat sink lid. The die is disposed on the circuit substrate and electrically connected with the circuit substrate. The die includes two first dies disposed side by side and separate from each other with a gap between two facing sidewalls of the two first dies. The frame structure is disposed on the circuit substrate and surrounding the die. The heat sink lid is disposed on the die and the frame structure. The head sink lid has a slit that penetrates through the heat sink lid in a thickness direction and exposes the gap between the two facing sidewalls of the two first dies.

Abstract: Described herein are methods of making (Z)-endoxifen, a salt thereof, crystalline forms of endoxifen, and compositions comprising them. Also described herein are crystalline forms of (Z)-endoxifen. A method of making (Z)-endoxifen may include one or more enrichment steps to enrich the amount of (Z)-endoxifen present in a composition. Enrichment may include one or more steps of crystallization, recrystallization, or fractional recrystallization to reduce the level of one or more impurities in the composition. These methods may be industrially scalable. Also described herein are compositions enriched for (Z)-endoxifen produced by the methods described herein.

Abstract: A resin composition includes 100 parts by weight of hydrocarbon resin polymers and 0.01 to 50 parts by weight of divinyl aromatic compound. A substrate structure includes a resin layer and a conductive layer disposed on the resin layer, wherein the resin layer is formed from the resin composition. A manufacturing method of the resin composition includes the following steps: providing a mixture, wherein the mixture includes a monovinyl aromatic compound and a divinyl aromatic compound, and optionally includes a bridged ring compound; polymerizing the mixture to form a crude composition; and purifying the crude composition to prepare the resin composition.

Abstract: Some implementations described herein provide techniques and apparatuses for an integrated circuit device including a trench capacitor structure that has a merged region. A material filling the merged region is different than a material that is included in electrode layers of the trench capacitor structure. Furthermore, the material filling the merged region includes a coefficient of thermal expansion and a modulus of elasticity that, in combination with the architecture of the trench capacitor structure, reduce thermally induced stresses and/or strains within the integrated circuit device relative to another integrated circuit device having a trench capacitor structure including a merged region and electrode layers of a same material.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a substrate comprising first opposing sidewalls defining a first trench and second opposing sidewalls defining a second trench laterally offset from the first trench. A stack of layers comprises a plurality of conductive layers and a plurality of dielectric layers alternatingly stacked with the conductive layers. The stack of layers comprises a first segment in the first trench and a second segment in the second trench. A first lateral distance between the first segment and the second segment aligned with a first surface of the substrate is greater than a second lateral distance between the first segment and the second segment below the first surface of the substrate.

Abstract: A diode array includes a substrate and a plurality of light emitting diodes disposed on the substrate and arranged in an array. Each of the light emitting diodes includes a stack of functional layers includes a first semiconductor layer, a second semiconductor layer, and a light emitting layer located between the first semiconductor layer and the second semiconductor layer. At least one of the light emitting diodes includes a first current limiting region covering at least a portion of the first semiconductor layer, the light emitting layer or the second semiconductor layer; a first electrode electrically connected to the first semiconductor layer; and a second electrode electrically connected to the second semiconductor layer, wherein the first electrode and the second electrode are disposed at the same side of the first semiconductor layer.

Abstract: Various embodiments of the present application are directed towards an integrated chip (IC). The IC comprises a trench capacitor overlying a substrate. The trench capacitor comprises a plurality of capacitor electrode structures, a plurality of warping reduction structures, and a plurality of capacitor dielectric structures. The plurality of capacitor electrode structures, the plurality of warping reduction structures, and the plurality of capacitor dielectric structures are alternatingly stacked and define a trench segment that extends vertically into the substrate. The plurality of capacitor electrode structures comprise a metal component and a nitrogen component. The plurality of warping reduction structures comprise the metal component, the nitrogen component, and an oxygen component.

Abstract: A semiconductor package includes a circuit substrate, a die, a frame structure, and a heat sink lid. The die is disposed on the circuit substrate and electrically connected with the circuit substrate. The die includes two first dies disposed side by side and separate from each other with a gap between two facing sidewalls of the two first dies. The frame structure is disposed on the circuit substrate and surrounding the die. The heat sink lid is disposed on the die and the frame structure. The head sink lid has a slit that penetrates through the heat sink lid in a thickness direction and exposes the gap between the two facing sidewalls of the two first dies.

Abstract: The invention discloses a method for preparing a polyester elastic conjugated yarn, comprising: forming a polyester yarn by using a polyester fiber as a raw material through a false twisting process; forming a thermoplastic polyester elastomer yarn by using a thermoplastic polyester elastomer (TPEE) as a raw material through an unwinding process; and combining the polyester yarn and the thermoplastic polyester elastomer yarn in a fiber blending process to obtain the polyester elastic conjugated yarn. The invention further discloses a polyester elastic conjugated yarn, and a yarn and a fabric comprising the polyester elastic conjugated yarn.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a capacitor over a substrate. The capacitor includes a plurality of conductive layers and a plurality of dielectric layers. The plurality of conductive layers and dielectric layers define a base structure and a first protrusion structure extending downward from the base structure towards a bottom surface of the substrate. The first protrusion structure comprises one or more surfaces defining a first cavity. A top of the first cavity is disposed below the base structure.

Abstract: The present disclosure provides systems, apparatus, methods, and computer-readable media that support adapting image processing based on the user activity performed while recording an image. In a first aspect, a method of image processing may include determining a type of activity based on sensor data, such as motion sensors and/or image sensor data. The type of activity may be provided to an image processing algorithm, such as an image/video stabilization algorithm, which adapts based on the activity type. For example, a rolling shutter correction may have a strength factor that is adapted to lower values when the type of activity is a panning motion when faces are present in the frame. As another example, another image stabilization (IS) algorithm such as an electronic image stabilization (EIS) algorithm may have adaptive behavior adjusted based on the type of activity. Other aspects and features are also claimed and described.

Abstract: A diode array includes a substrate and a plurality of light emitting diodes disposed on the substrate and arranged in an array. Each of the light emitting diodes includes a stack of functional layers includes a first semiconductor layer, a second semiconductor layer, and a light emitting layer located between the first semiconductor layer and the second semiconductor layer. At least one of the light emitting diodes includes a first current limiting region covering at least a portion of the first semiconductor layer, the light emitting layer or the second semiconductor layer; a first electrode electrically connected to the first semiconductor layer; and a second electrode electrically connected to the second semiconductor layer, wherein the first electrode and the second electrode are disposed at the same side of the first semiconductor layer.

Abstract: The present invention provides an application of genistein and its phosphate ester derivative for treating or preventing diseases mediated by the cannabinoid receptor type 1 (CB1 receptor) in an individual. The present invention also provides a pharmaceutical composition for treating or preventing CB1 receptor-mediated diseases, comprising an effective amount of genistein and its phosphate ester derivative.