Abstract: An efficient chip stacking structure is described that includes a leadframe having two surfaces to each of which can be attached stacks of chips. A chip stack can be formed by placing a chip active surface on a back surface of another chip. Electrical connections between chips and leads on the leadframe are facilitated by bonding pads on chip active surfaces and by via that extend from the bonding pads through the chips to the back surfaces.

Abstract: A multi-chip stacked package structure, including a leadframe base thin package structure with two or more chips in the stacking structure, is provided that is capable of including two or more stacked chips that reduce the total stacking thickness. The package structure also reduces stacking thickness by achieving stacking of four or more chips into the area of a thin small outline package structure.

Abstract: A semiconductor packaging device comprises a carrier having at least a cavity/a slot thereon, at least a chip has a back surface and an active surface with a plurality of first bonding pads. The chip is affixed to the cavity to expose the active surface. A first insulating layer is on the active surface and the carrier comprises first plating through holes connected to first bonding pads and via the first insulating layer. A multi-layer structure on the first insulating layer comprises a plurality of conductive layout lines, second plating through holes therein, and a second insulating layer, exposed ball pads, and flip-chip pads thereon. The first plating through holes are electrically connected with the conductive layout lines, the second plating through holes, the exposed ball pads, and the flip-chip pads. The first solder balls are affixed to the ball pads.

Abstract: A semiconductor packaging device comprises a carrier having at least a cavity or a slot thereon. At least a chip has a back surface and an active surface with a plurality of first bonding pads. The chip is affixed to the cavity to expose the active surface. A first insulating layer is on the active surface and the carrier, which comprises first via-conductor connected to first bonding pads and via the first insulating layer. A multi-layer structure on the first insulating layer comprises a plurality of conductive layout lines, second via-conductor therein, and a second insulating layer, exposed ball pads, and flip-chip pads thereon. The first via-conductor are electrically connected with the conductive layout lines, the second via-conductor, the exposed ball pads, and the flip-chip pads. The first solder balls are affixed to the ball pads, and at least a second chip is affixed to the flip-chip pads through a plurality of second solder balls.

Abstract: An image sensor package having at least one chip supporting bar secured to a top surface of an image sensor chip. The thickness of the chip supporting bar is absorbed within a vertical dimension of wire loops that connect bonding pads to leads so that the chip supporting bar does not contribute to the thickness of the image sensor package. An exposed back surface of the image sensor chip enhances thermal dissipation.

Abstract: A thin stacked image sensor package containing an image sensor chip and a peripheral chip. A support pad for the peripheral chip adheres to a top surface of the peripheral chip, eliminating the need for a support member that otherwise would contribute to the thickness of the package. Thermal dissipation is enhanced by exposing surfaces including a back surface of the peripheral chip.

Abstract: A semiconductor packaging device has a carrier having at least a portion configured for containing a chip. The chip, affixing to the portion with sidewall, has a back surface an active surface, which multitudes of bonding pads are on the active surface. One insulating layer on the active surface and carrier has multitudes of conductive holes corresponding to the first bonding pads. A multi-layer structure on the insulating layer is configured for providing electrical connection to the conductive holes. Another insulating layer, affixed on one of the carrier and the multi-layer structure, has another conductive holes electrically connected to the conductive holes. Multitudes of solder balls, on at least one of the carrier and latter insulating layer, electrically connect the latter conductive holes.

Abstract: A stacking structure is described that permits stacking of electrical components with no requirement for an ancillary stacking framework. Electrical components are fabricated with inner and outer lead portions that provide connection to a substrate and to other electrical components in a stack.

Abstract: A stacking structure is described that permits stacking of electrical components with no requirement for an ancillary stacking framework. Electrical components are fabricated with inner and outer lead portions that provide connection to a substrate and to other electrical components in a stack.

Abstract: A semiconductor packaging structure. The structure comprises a chip, a lead frame, and a plurality of wires. The chip comprises an active surface and an opposing non-active surface, the active surface comprising a central area and a peripheral area having a plurality of bonding pads. The lead frame comprises a plurality of the leads, a plurality of tie bars, and a chip paddle. The tie bars is connected with the chip paddle and attached to the active surface of the chip in such a way as to avoid contact with the bonding pads. As well, the wires electrically connect with the bonding pad and the leads.

Abstract: A dual chips stacked packaging structure. A first chip comprises an active surface and an opposing non-active surface, the active surface consisting of a central area and a peripheral area having a plurality of first bonding pads. A lead frame comprises a plurality of leads and a chip paddle having a first adhering surface and a second adhering surface, with the first adhering surface adhering to the active surface of the first chip in such a way as to avoid contact with the first bonding pads. A second chip comprises an active surface and an opposing non-active surface connecting with the second adhering surface of the chip paddle, and the active surface consisting of a central area and a peripheral area having a plurality of second bonding pads. Parts of the wires electrically connect with the first bonding pad and the leads, and parts of the wires electrically connect with the second bonding pad and the leads.

Abstract: A stacking multi-chip device comprises a substrate having a recess, stud bumpers or conductive stud strips thereon. A low die has a back surface affixed in the recess or the substrate, and has a first active surface comprising a plurality of bonding pads. The bonding pads of the low die have a set of elongate conductors connected to the substrate. An upper die has a back surface and a second active surface comprising a plurality of bonding pads. The bonding pads of the upper die have a plurality of stud bumpers connected to the stud bumpers, conductive stud strips, or the substrate by the method of reflow or anti-tropic conductive film. The second active surface is faced towards said first active surface and is offset stacked atop the low die to expose all bonding pads.

Abstract: A semiconductor package body having a lead frame. The lead frame is electrically connected to a semiconductor chip via at least one bonding wire in the semiconductor package body. The lead frame has a die pedestal having a first surface and a second surface opposite each other, a base pad disposed outside the die pedestal, at least one connecting part providing a connection between the die pedestal and the base pad, and a plurality of leads. Each lead has an electrical connecting portion and a connecting foot portion, in which the electrical connecting portion is electrically connected to the semiconductor chip via the bonding wire, and the connecting foot portion is exposed to the exterior of the semiconductor package body, thereby providing enhanced heat dissipation.

Abstract: A stacked semiconductor packaging device consists of at least a stacked multi-chip device comprising a substrate. A first chip has a back surface faced towards the substrate and an active surface comprising a plurality of bonding pads which have a first set of elongate conductors connected to the substrate. A second chip has another back surface and another active surface comprising a plurality of bonding pads which have a second set of elongate conductors connected to the substrate. The active surface of the second chip is faced towards the active surface of said first chip and is stacked atop the first chip so as to expose all of the bonding pads. The face-to-face arrangement of the first chip and the second chip can reduce the whole packing height.

Abstract: A semiconductor packaging device comprises a carrier having at least a cavity or a slot thereon. At least a chip has a back surface and an active surface with a plurality of first bonding pads. The chip is affixed to the cavity to expose the active surface. A first insulating layer is on the active surface and the carrier, which comprises first via-conductor connected to first bonding pads and via the first insulating layer. A multi-layer structure on the first insulating layer comprises a plurality of conductive layout lines, second via-conductor therein, and a second insulating layer, exposed ball pads, and flip-chip pads thereon. The first via-conductor are electrically connected with the conductive layout lines, the second via-conductor, the exposed ball pads, and the flip-chip pads. The first solder balls are affixed to the ball pads, and at least a second chip is affixed to the flip-chip pads through a plurality of second solder balls.

Abstract: A stacked semiconductor packaging device consists of at least a stacked multi-chip device comprising a substrate. A first chip has a back surface faced towards the substrate and an active surface comprising a plurality of bonding pads which have a first set of elongate conductors connected to the substrate. A second chip has another back surface and another active surface comprising a plurality of bonding pads which have a second set of elongate conductors connected to the substrate. The active surface of the second chip is faced towards the active surface of said first chip and is stacked atop the first chip so as to expose all of the bonding pads. The face-to-face arrangement of the first chip and the second chip can reduce the whole packing height.

Abstract: A semiconductor packaging device comprises a carrier having at least a cavity or a slot thereon. At least a chip has a back surface and an active surface with a plurality of first bonding pads. The chip is affixed to the cavity to expose the active surface. A first insulating layer is on the active surface and the carrier, which comprises first plating through holes connected to first bonding pads and via the first insulating layer. A multi-layer structure is on the first insulating layer, which comprises conductive layout lines, second plating through holes therein, and a second insulating layer and exposed ball pads thereon. The first plating through holes are electrically connected with the conductive layout lines, the second plating through holes, and the exposed ball pads. A plurality of solder balls are affixed to the ball pads. Such architecture integrates the redistribution and fan-out process, which simplifies the conventional process for flip-chip ball grid array.

Abstract: A structure of a stacked-type multi-chip stack package of the leadframe, the shape of the stair-like inner leads can be regulated for the high and the amount of stacked chips and to match different bonding technology. The process for forming the present structure can be easily performed by visible equipment and materials, and the present structure can raise the reliability of bonding process. The present invention can stack multi-chip (more than two).

Abstract: The present invention provides a structure and a method for multi-chip stack package. The present invention uses the liquid insulating epoxy to adhere and stack chips. The liquid insulating epoxy is filled the space between chips and metal wires bonded thereon and the liquid insulating epoxy is higher than the high of the arc of those metal wires, so it can increase the reliability of stacking and bonding process. The present invention can stack multi-chip (more than two) bycontrolling the arc height of the wire and the thickness of the chip. The present can easily perform by visible equipment and materials.

Abstract: The present invention provides a structure and a method for multi-chip stack package. The present invention uses the liquid insulating epoxy to adhere and stack chips. The liquid insulating epoxy is filled the space between chips and metal wires bonded thereon and the liquid insulating epoxy is higher than the high of the arc of those metal wires, so it can increase the reliability of stacking and bonding process. The present invention can stack multi-chip (more than two) by controlling the arc height of the wire and the thickness of the chip. The present can easily perform by visible equipment and materials.