Patents by Inventor Chen Liang

Chen Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11456256
    Abstract: A semiconductor device includes a semiconductor substrate, a dielectric structure, an electrical insulating and thermal conductive layer and a circuit layer. The electrical insulating and thermal conductive layer is disposed over the semiconductor substrate. The dielectric structure is disposed over the electrical insulating and thermal conductive layer, wherein a thermal conductivity of the electrical insulating and thermal conductive layer is substantially greater than a thermal conductivity of the dielectric structure. The circuit layer is disposed in the dielectric structure.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: September 27, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hang Tung, Chen-Hua Yu, Tung-Liang Shao, Su-Chun Yang, Wen-Lin Shih
  • Publication number: 20220301889
    Abstract: Integrated circuit packages and methods of forming the same are disclosed. A first die is mounted on a first side of a workpiece, the workpiece including a second die. The workpiece is mounted to a front side of a package substrate, where the first die is at least partially disposed in a through hole in the package substrate. A heat dissipation feature may be attached on a second side of the workpiece. An encapsulant may be formed on the front side of the package substrate around the workpiece.
    Type: Application
    Filed: June 10, 2022
    Publication date: September 22, 2022
    Inventors: Chen-Hua Yu, Chien-Hsun Lee, Chi-Yang Yu, Jung Wei Cheng, Chin-Liang Chen
  • Patent number: 11451066
    Abstract: Provided are a control method and a device for active power of a wind power plant cluster. The wind power plant cluster includes wind power plants of m priorities, wherein m is a positive integer. The control method includes: monitoring the consumption capability of a power grid in real time, and determining object active power of the wind power plant cluster according to the consumption capability of the power grid; determining a command active power of the wind power plant within each priority according to the object active power of the wind power plant cluster in a descending order of the priorities; and controlling real active power of the wind power plant within each priority according to the command active power.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: September 20, 2022
    Inventors: Jingran Wang, Bingxu Zhai, Rongfu Sun, Haibo Lan, Ruoyang Wang, Ran Ding, Haixiang Xu, Zhifeng Liang, Tao Lun, Zongxiang Lu, Chen Xu, Li Shu, Yu Shen, Xiaobo Wu
  • Patent number: 11444421
    Abstract: A power adapter is disclosed with retractable prongs to engage an outlet and obtain power therefrom, when extended, and be partially or entirely within the housing of the power adapter when retracted. To ensure safe operation, a channel is provided within the power adapter to accommodate the prongs when retracted and to accommodate the prongs travel as they pivot between extended and retracted. The channel is width-limited and/or has a length to make it impossible or, at least, exceptionally difficult for a human finger to come into contact with the prongs while the prongs are extended and sufficiently engaged with an outlet to obtain power therefrom.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: September 13, 2022
    Assignee: Flex Ltd.
    Inventors: Li-Wei Liang, Yungsung Chen, Jungchih Hsu
  • Patent number: 11444206
    Abstract: A manufacturing method of a semiconductor structure including the following steps is provided: forming a first metal layer on a substrate; forming an insulating layer on the first metal layer; forming an oxide semiconductor material layer on the insulating layer; performing an annealing treatment to the oxide semiconductor material layer; forming an etch stopping material layer on the oxide semiconductor material layer; forming a photoresist material layer on the etch stopping material layer and defining thereof with a half tone photomask to form a photoresist pattern; using the photoresist pattern as a mask, patterning the etch stopping material layer to form an etch stopping pattern, and patterning the oxide semiconductor material layer to form an oxide semiconductor layer; removing the photoresist pattern; using the etch stopping pattern as the mask, patterning the insulating layer; forming a second metal layer on the etch stopping pattern; and patterning the oxide semiconductor layer.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: September 13, 2022
    Assignee: Au Optronics Corporation
    Inventors: Po-Liang Yeh, Chen-Chung Wu, De-Zhang Deng, Chia-Ming Chang
  • Patent number: 11444169
    Abstract: A transistor device with a recessed gate structure is provided. In some embodiments, the transistor device comprises a semiconductor substrate comprising a device region surrounded by an isolation structure and a pair of source/drain regions disposed in the device region and laterally spaced apart one from another in a first direction. A gate structure overlies the device region and the isolation structure and arranged between the pair of source/drain regions. The gate structure comprises a pair of recess regions disposed on opposite sides of the device region in a second direction perpendicular to the first direction. A channel region is disposed in the device region underneath the gate structure. The channel region has a channel width extending in the second direction from one of the recess regions to the other one of the recess regions.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: September 13, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Liang Chu, Chien-Chih Chou, Chih-Chang Cheng, Yi-Huan Chen, Kong-Beng Thei, Ming-Ta Lei, Ruey-Hsin Liu, Ta-Yuan Kung
  • Patent number: 11443981
    Abstract: A bonding method of package components and a bonding apparatus are provided. The method includes: providing at least one first package component and a second package component, wherein the at least one first package component has first electrical connectors and a first dielectric layer at a bonding surface of the at least one first package component, and the second package component has second electrical connectors and a second dielectric layer at a bonding surface of the second package component; bringing the at least one first package component and the second package component in contact, such that the first electrical connectors approximate or contact the second electrical connectors; and selectively heating the first electrical connectors and the second electrical connectors by electromagnetic induction, in order to bond the first electrical connectors with the second electrical connectors.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: September 13, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Li Hsiao, Chih-Hang Tung, Chen-Hua Yu, Tung-Liang Shao, Su-Chun Yang
  • Publication number: 20220285310
    Abstract: A method includes picking up a first package component, removing an oxide layer on an electrical connector of the first package component, placing the first package component on a second package component after the oxide layer is removed, and bonding the first package component to the second package component.
    Type: Application
    Filed: May 23, 2022
    Publication date: September 8, 2022
    Inventors: Chen-Hua Yu, Ying-Jui Huang, Chih-Hang Tung, Tung-Liang Shao, Ching-Hua Hsieh, Chien Ling Hwang, Yi-Li Hsiao, Su-Chun Yang
  • Patent number: 11437347
    Abstract: A hybrid memory structure including a substrate, a flash memory, a first resistive random access memory (RRAM), and a second RRAM is provided. The flash memory is located on the substrate. The flash memory includes a gate, a first doped region, and a second doped region. The gate is located on the substrate. The first doped region is located in the substrate on one side of the gate. The second doped region is located in the substrate on another side of the gate. The first RRAM is electrically connected to one of the gate, the first doped region, and the second doped region. The second RRAM is electrically connected to another of the gate, the first doped region, and the second doped region.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: September 6, 2022
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Chen-Liang Ma, Zih-Song Wang
  • Publication number: 20220279466
    Abstract: A device and method for vehicle-to-vehicle communication. The method includes: a source device sends a request message to a base station, the request message being used for requesting the base station to allocating a resource; a node device that is synchronous with the source device sends synchronous information to at least one target device, so that the at least one target device establishes time synchronization with the source device according to the synchronous information, wherein the node device is a road-side device or an in-car device capable of communicating; the source device informs the at least one target device of a resource allocated by the base station; and the source device sends service information to the at least one target device by utilizing the resource.
    Type: Application
    Filed: May 18, 2022
    Publication date: September 1, 2022
    Applicant: Sony Group Corporation
    Inventors: Yanzhao HOU, Qimei CUI, Shiyu ZHANG, Shiwei CAO, Hui LIANG, Qinyan JIANG, Xin GUO, Chen SUN
  • Patent number: 11427094
    Abstract: A computer-implemented method for prioritizing one or more electric vehicles that need a battery charge while driving. The method receives a wireless communication between one or more electric vehicles on a section of the roadway. The method further communicates a risk score between the one or more electric vehicles, based on a charging regulation model. The method further prioritizes a need for a battery charge, for the one or more electric vehicles on the section of the roadway, based on the communicated risk score. The method further engages one or more wireless charging points on the section of the roadway, with the one or more electric vehicles, based on the prioritized need for a battery charge.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: August 30, 2022
    Assignee: Kyndryl, Inc.
    Inventors: Michael Treadway, Craig M. Trim, Chen Liang, Shikhar Kwatra, Jeremy R. Fox, Joseph Blee
  • Patent number: 11422473
    Abstract: A method for improving a process model by measuring a feature on a printed design that was constructed based in part on a target design is disclosed. The method includes obtaining a) an image of the printed design from an image capture device and b) contours based on shapes in the image. The method also includes identifying, by a pattern recognition program, patterns on the target design that include the feature and determining coordinates, on the contours, that correspond to the feature. The method further includes improving the process model by at least a) providing a measurement of the feature based on the coordinates and b) calibrating the process model based on a comparison of the measurement with a corresponding feature in the target design.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: August 23, 2022
    Assignee: ASML Netherlands B.V.
    Inventors: Jiao Liang, Chen Zhang, Qiang Zhang, Yunbo Guo
  • Publication number: 20220246574
    Abstract: A method includes patterning a cavity through a first passivation layer of a first package component, the first package component comprising a first semiconductor substrate and bonding the first package component to a second package component. The second package component comprises a second semiconductor substrate and a second passivation layer. Bonding the first package component to the second package component comprises directly bonding the first passivation layer to the second passivation layer; and reflowing a solder region of a conductive connector disposed in the cavity to electrically connect the first package component to the second package component.
    Type: Application
    Filed: April 25, 2022
    Publication date: August 4, 2022
    Inventors: Chen-Hua Yu, Tung-Liang Shao, Chih-Hang Tung
  • Patent number: 11393809
    Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: July 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Fu Hsu, Ta-Yuan Kung, Chen-Liang Chu, Chih-Chung Tsai
  • Patent number: 11390520
    Abstract: In an embodiment, a system includes: a chamber; and a magnetic assembly contained within the chamber. The magnetic assembly comprises: an inner magnetic portion comprising first magnets; and an outer magnetic portion comprising second magnets. At least two adjacent magnets, of either the first magnets or the second magnets, have different vertical displacements, and the magnetic assembly is configured to rotate around an axis to generate an electromagnetic field that moves ions toward a target region within the chamber.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: July 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Fang Chung, Wen-Cheng Cheng, Tsez-Chong Tsai, Shuen-Liang Tseng, Szu-Hsien Lo, Po-Wen Yang, Ming-Jie He
  • Publication number: 20220223528
    Abstract: A method for semiconductor manufacturing is disclosed. The method includes receiving a device having a first surface through which a first metal or an oxide of the first metal is exposed. The method further includes depositing a dielectric film having Si, N, C, and O over the first surface such that the dielectric film has a higher concentration of N and C in a first portion of the dielectric film near the first surface than in a second portion of the dielectric film further away from the first surface than the first portion. The method further includes forming a conductive feature over the dielectric film. The dielectric film electrically insulates the conductive feature from the first metal or the oxide of the first metal.
    Type: Application
    Filed: April 4, 2022
    Publication date: July 14, 2022
    Inventors: Cheng-Yi Wu, Li-Hsuan Chu, Ching-Wen Wen, Chia-Chun Hung, Chen Liang Chang, Chin-Szu Lee, Hsiang Liu
  • Publication number: 20220223391
    Abstract: A method for modifying magnetic field distribution in a deposition chamber is disclosed. The method includes the operations of providing a target magnetic field distribution, removing a first plurality of fixed magnets in the deposition chamber, replacing each of the first plurality of fixed magnets with respective ones of a second plurality of magnets, performing at least one of adjusting a position of at least one of the second plurality of the magnets, and adjusting a size of at least one of the second plurality of magnets, adjusting a magnetic flux of at least one of the second plurality of magnets, measuring the magnetic field distribution in the deposition chamber, and comparing the measured magnetic field distribution in the deposition chamber with the target magnetic field distribution.
    Type: Application
    Filed: March 31, 2022
    Publication date: July 14, 2022
    Inventors: Ming-Jie HE, Shawn YANG, Szu-Hsien LO, Shuen-Liang TSENG, Wen-Cheng CHENG, Chen-Fang CHUNG, Chia-Lin HSUEH, Kuo-Pin CHUANG
  • Patent number: 11387118
    Abstract: Integrated circuit packages and methods of forming the same are disclosed. A first die is mounted on a first side of a workpiece, the workpiece including a second die. The workpiece is mounted to a front side of a package substrate, where the first die is at least partially disposed in a through hole in the package substrate. A heat dissipation feature may be attached on a second side of the workpiece. An encapsulant may be formed on the front side of the package substrate around the workpiece.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: July 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chien-Hsun Lee, Chi-Yang Yu, Jung Wei Cheng, Chin-Liang Chen
  • Patent number: 11385175
    Abstract: A calibration method includes: acquiring eight error models obtained after a preliminary calibration of a Terahertz frequency band system; based on the eight error models, determining a first mathematical model according to a first S parameter related to a first calibration piece, the first mathematical model comprising parallel crosstalk terms between probes, and determining a second mathematical model according to a second S parameter related to a second calibration piece, the second mathematical model comprising series crosstalk terms between the probes; determining a third mathematical model according to a third S parameter related to a measured piece; and solving and obtaining a Z parameter of the measured piece based on the first mathematical model, the second mathematical model and the third mathematical model, and acquiring an S parameter of the measured piece according to the Z parameter of the measured piece.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: July 12, 2022
    Assignee: THE 13TH RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Yibang Wang, Aihua Wu, Faguo Liang, Chen Liu, Peng Luan, Ye Huo, Jing Sun, Yanli Li
  • Patent number: D962799
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: September 6, 2022
    Assignee: China Meteorological Administration Meteorological Observation Center
    Inventors: Yuchun Gao, Chen Li, Yubao Chen, Yingchun Chen, Changxing Li, Hu Chen, Xiaopeng Wang, Jianbing Lu, Xu Han, Zhichao Bu, Haihe Liang, Nan Shao