Patents by Inventor Chen Liang

Chen Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11444169
    Abstract: A transistor device with a recessed gate structure is provided. In some embodiments, the transistor device comprises a semiconductor substrate comprising a device region surrounded by an isolation structure and a pair of source/drain regions disposed in the device region and laterally spaced apart one from another in a first direction. A gate structure overlies the device region and the isolation structure and arranged between the pair of source/drain regions. The gate structure comprises a pair of recess regions disposed on opposite sides of the device region in a second direction perpendicular to the first direction. A channel region is disposed in the device region underneath the gate structure. The channel region has a channel width extending in the second direction from one of the recess regions to the other one of the recess regions.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: September 13, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Liang Chu, Chien-Chih Chou, Chih-Chang Cheng, Yi-Huan Chen, Kong-Beng Thei, Ming-Ta Lei, Ruey-Hsin Liu, Ta-Yuan Kung
  • Patent number: 11437347
    Abstract: A hybrid memory structure including a substrate, a flash memory, a first resistive random access memory (RRAM), and a second RRAM is provided. The flash memory is located on the substrate. The flash memory includes a gate, a first doped region, and a second doped region. The gate is located on the substrate. The first doped region is located in the substrate on one side of the gate. The second doped region is located in the substrate on another side of the gate. The first RRAM is electrically connected to one of the gate, the first doped region, and the second doped region. The second RRAM is electrically connected to another of the gate, the first doped region, and the second doped region.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: September 6, 2022
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Chen-Liang Ma, Zih-Song Wang
  • Patent number: 11427094
    Abstract: A computer-implemented method for prioritizing one or more electric vehicles that need a battery charge while driving. The method receives a wireless communication between one or more electric vehicles on a section of the roadway. The method further communicates a risk score between the one or more electric vehicles, based on a charging regulation model. The method further prioritizes a need for a battery charge, for the one or more electric vehicles on the section of the roadway, based on the communicated risk score. The method further engages one or more wireless charging points on the section of the roadway, with the one or more electric vehicles, based on the prioritized need for a battery charge.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: August 30, 2022
    Assignee: Kyndryl, Inc.
    Inventors: Michael Treadway, Craig M. Trim, Chen Liang, Shikhar Kwatra, Jeremy R. Fox, Joseph Blee
  • Patent number: 11393809
    Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: July 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Fu Hsu, Ta-Yuan Kung, Chen-Liang Chu, Chih-Chung Tsai
  • Publication number: 20220223528
    Abstract: A method for semiconductor manufacturing is disclosed. The method includes receiving a device having a first surface through which a first metal or an oxide of the first metal is exposed. The method further includes depositing a dielectric film having Si, N, C, and O over the first surface such that the dielectric film has a higher concentration of N and C in a first portion of the dielectric film near the first surface than in a second portion of the dielectric film further away from the first surface than the first portion. The method further includes forming a conductive feature over the dielectric film. The dielectric film electrically insulates the conductive feature from the first metal or the oxide of the first metal.
    Type: Application
    Filed: April 4, 2022
    Publication date: July 14, 2022
    Inventors: Cheng-Yi Wu, Li-Hsuan Chu, Ching-Wen Wen, Chia-Chun Hung, Chen Liang Chang, Chin-Szu Lee, Hsiang Liu
  • Publication number: 20220180207
    Abstract: Provided is an end-to-end pipeline (e.g., which may be implemented in TensorFlow) which leverages a specialized search space to generate custom models which provide improved time series prediction.
    Type: Application
    Filed: March 24, 2021
    Publication date: June 9, 2022
    Inventors: Chen Liang, Da Huang, Yifeng Lu
  • Patent number: 11348043
    Abstract: A method, system and computer program product for automatically distributing tasks within a group includes identifying, by one or more processors, first data associated with each member of a group. The one or more processors identify second data associated with demands for the group, calculate a total work time for each member of the group using the first data, identify conflicts between the total work time for each member of the group and the second data, and based on the identified conflict, distribute tasks among members of the group.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: May 31, 2022
    Assignee: International Business Machines Corporation
    Inventors: Jeremy R. Fox, Kelley Anders, Chen Liang, Andrew Charles Whiriskey
  • Publication number: 20220144874
    Abstract: The disclosure provides a method for preparing an amphiphilic lignin nanomaterial based on pulping black liquor, an amphiphilic lignin nanomaterial, and an oil sludge detergent. In the disclosure, physical treatments such as ball milling and high-pressure jet homogenization treatment are conducted on alkali lignin at the early stage to adjust the molecular weight and size of alkali lignin and thus to give alkali lignin nanoparticles with uniform particle sizes; and on this basis, a chemical treatment such as alkylation grafting modification is conducted to give amphiphilic lignin nanoparticles with both hydrophilicity and lipophilicity. Due to the nano-size effect, the amphiphilic lignin nanomaterial has a significantly-increased specific surface area (SSA) and effectively-improved surface properties, which can reduce the oil-water interfacial tension, and emulsify the crude oil and peel off the crude oil from the surface of rock particles, so as to achieve the purpose of oil-solid separation.
    Type: Application
    Filed: November 11, 2020
    Publication date: May 12, 2022
    Inventors: Chengrong QIN, Jian ZHANG, Chen LIANG, Shuangquan YAO, Xinliang LIU, Zhiwei WANG, Wei LI, Jiulong SHA
  • Patent number: 11296027
    Abstract: A method for semiconductor manufacturing is disclosed. The method includes receiving a device having a first surface through which a first metal or an oxide of the first metal is exposed. The method further includes depositing a dielectric film having Si, N, C, and O over the first surface such that the dielectric film has a higher concentration of N and C in a first portion of the dielectric film near the first surface than in a second portion of the dielectric film further away from the first surface than the first portion. The method further includes forming a conductive feature over the dielectric film. The dielectric film electrically insulates the conductive feature from the first metal or the oxide of the first metal.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: April 5, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yi Wu, Li-Hsuan Chu, Ching-Wen Wen, Chia-Chun Hung, Chen Liang Chang, Chin-Szu Lee, Hsiang Liu
  • Publication number: 20220090204
    Abstract: The present invention discloses a reference DNA and the use thereof, wherein the reference DNA is selected from the group consisting of: (i) DNA fragment 1: characterized in that it carries a defined gene mutation and at least one another artificially altered base X2, wherein, as compared to a wild type of the gene, at least one defined base X1 in the defined gene mutation undergoes a mutation associated with the occurrence, diagnosis, and/or treatment (such as a target targeted by a medicament) of a disease (such as a tumor), wherein the mutation is a substitution mutation, a deletion mutation, and/or an insertion mutation, and the artificially altered base X2 is different from the mutant base X1 which is contained in the DNA of a sample to be detected and defined to be associated with the occurrence, diagnosis and/or treatment of a disease, (ii) DNA fragment 2: characterized in that it differs from the DNA fragment 1 only in that it does not comprise the defined base X1 mutation, or (iii) a mixture of th
    Type: Application
    Filed: November 20, 2019
    Publication date: March 24, 2022
    Inventors: Shuwei Yang, Liancheng Huang, Chen Liang, Yunyi Chen, Haiying Chen
  • Publication number: 20220068878
    Abstract: A hybrid memory structure including a substrate, a flash memory, a first resistive random access memory (RRAM), and a second RRAM is provided. The flash memory is located on the substrate. The flash memory includes a gate, a first doped region, and a second doped region. The gate is located on the substrate. The first doped region is located in the substrate on one side of the gate. The second doped region is located in the substrate on another side of the gate. The first RRAM is electrically connected to one of the gate, the first doped region, and the second doped region. The second RRAM is electrically connected to another of the gate, the first doped region, and the second doped region.
    Type: Application
    Filed: September 28, 2020
    Publication date: March 3, 2022
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Chen-Liang Ma, Zih-Song Wang
  • Publication number: 20220043981
    Abstract: The present disclosure is directed to systems and methods for performing reading comprehension with machine learning. More specifically, the present disclosure is directed to a Neural Symbolic Reader (example implementations of which may be referred to as NeRd), which includes a reader to encode the passage and question, and a programmer to generate a program for multi-step reasoning. By using operators like span selection, the program can be executed over a natural language text passage to generate an answer to a natural language text question. NeRd is domain-agnostic such that the same neural architecture works for different domains. Further, NeRd it is compositional such that complex programs can be generated by compositionally applying the symbolic operators.
    Type: Application
    Filed: August 6, 2020
    Publication date: February 10, 2022
    Inventors: Chen Liang, Wei Yu, Quoc V. Le, Xinyun Chen, Dengyong Zhou
  • Patent number: 11224811
    Abstract: An information display method in a battle game is provided, applied to a terminal on which a first client is run, the method including: obtaining a first combat power value of a first game role; receiving a second combat power value of a second game role controlled by a second client or an Artificial Intelligence (AI) program; obtaining, according to the second combat power value and the first combat power value, a combat power difference between the second game role and the first game role; determining, according to the combat power difference, a display mode of the second combat power value; and displaying a battle interface, the battle interface including an object corresponding to the second game role and the second combat power value displayed in the display mode, the second combat power value being located in a peripheral position of the object corresponding to the second game role.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: January 18, 2022
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LTD
    Inventors: Cheng Chi Yu, Chen Liang
  • Patent number: 11152306
    Abstract: A method for semiconductor manufacturing is disclosed. The method includes receiving a device having a first surface through which a first metal or an oxide of the first metal is exposed. The method further includes depositing a dielectric film having Si, N, C, and O over the first surface such that the dielectric film has a higher concentration of N and C in a first portion of the dielectric film near the first surface than in a second portion of the dielectric film further away from the first surface than the first portion. The method further includes forming a conductive feature over the dielectric film. The dielectric film electrically insulates the conductive feature from the first metal or the oxide of the first metal.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: October 19, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yi Wu, Li-Hsuan Chu, Ching-Wen Wen, Chia-Chun Hung, Chen Liang Chang, Chin-Szu Lee, Hsiang Liu
  • Publication number: 20210300189
    Abstract: A computer-implemented method for prioritizing one or more electric vehicles that need a battery charge while driving. The method receives a wireless communication between one or more electric vehicles on a section of the roadway. The method further communicates a risk score between the one or more electric vehicles, based on a charging regulation model. The method further prioritizes a need for a battery charge, for the one or more electric vehicles on the section of the roadway, based on the communicated risk score. The method further engages one or more wireless charging points on the section of the roadway, with the one or more electric vehicles, based on the prioritized need for a battery charge.
    Type: Application
    Filed: March 26, 2020
    Publication date: September 30, 2021
    Inventors: Michael Treadway, Craig M. Trim, Chen Liang, Shikhar Kwatra, Jeremy R. Fox, JOSEPH BLEE
  • Publication number: 20210302182
    Abstract: A computer-implemented method for determining whether an electric vehicle (EV) requires a current charge. The method analyzes a set of EV data, wherein the set of EV data comprises a battery level, a destination, a current position, and a predicted arrival time to the destination. The method further constructs a charging regulation model for the EV, based on the analyzed set of EV data. The method further computes a risk score pertaining to charging the EV, based on the constructed charging regulation model for the EV, and determines whether the EV requires a current charge based on the computed risk score. The method further engages one or more wireless charging points on a roadway, if the computed risk score is below a threshold value.
    Type: Application
    Filed: March 26, 2020
    Publication date: September 30, 2021
    Inventors: Michael Treadway, Craig M. Trim, Chen Liang, Shikhar Kwatra, Jeremy R. Fox, JOSEPH BLEE
  • Patent number: 11132436
    Abstract: A method including detecting, in response to a design file uploaded by a development device, validity of an actual constraint file included in the design file and corresponding to an FPGA of the FPGA cloud host; synthesis processing the design file in response to detecting that the actual constraint file is valid; and writing a burner file obtained from the synthesis processing into the FPGA. The validity of the actual constraint file is detected to prevent a malicious attack of a user to FPGA hardware.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: September 28, 2021
    Assignee: Alibaba Group Holding Limited
    Inventor: Chen Liang
  • Publication number: 20210273069
    Abstract: A transistor device with a recessed gate structure is provided. In some embodiments, the transistor device comprises a semiconductor substrate comprising a device region surrounded by an isolation structure and a pair of source/drain regions disposed in the device region and laterally spaced apart one from another in a first direction. A gate structure overlies the device region and the isolation structure and arranged between the pair of source/drain regions. The gate structure comprises a pair of recess regions disposed on opposite sides of the device region in a second direction perpendicular to the first direction. A channel region is disposed in the device region underneath the gate structure. The channel region has a channel width extending in the second direction from one of the recess regions to the other one of the recess regions.
    Type: Application
    Filed: July 15, 2020
    Publication date: September 2, 2021
    Inventors: Chen-Liang Chu, Chien-Chih Chou, Chih-Chang Cheng, Yi-Huan Chen, Kong-Beng Thei, Ming-Ta Lei, Ruey-Hsin Liu, Ta-Yuan Kung
  • Publication number: 20210256390
    Abstract: A method for receiving training data for training a neural network to perform a machine learning task and for searching for, using the training data, an optimized neural network architecture for performing the machine learning task is described. Searching for the optimized neural network architecture includes: maintaining population data; maintaining threshold data; and repeatedly performing the following operations: selecting one or more candidate architectures from the population data; generating a new architecture from the one or more selected candidate architectures; for the new architecture: training a neural network having the new architecture until termination criteria for the training are satisfied; and determining a final measure of fitness of the neural network having the new architecture after the training; and adding data defining the new architecture and the final measure of fitness for the neural network having the new architecture to the population data.
    Type: Application
    Filed: May 3, 2021
    Publication date: August 19, 2021
    Inventors: David Martin Dohan, David Richard So, Chen Liang, Quoc V. Le
  • Publication number: 20210256313
    Abstract: Methods and systems for learning policies using sparse and underspecified rewards. One of the methods includes training the policy jointly with an auxiliary reward function having a plurality of auxiliary reward parameters, the auxiliary reward function being configured to map, in accordance with the auxiliary reward parameters, trajectory features of at least a trajectory to an auxiliary reward value that indicates how well the trajectory performed a task in response to a context input.
    Type: Application
    Filed: February 19, 2021
    Publication date: August 19, 2021
    Inventors: Rishabh Agarwal, Chen Liang, Dale Eric Schuurmans, Mohammad Norouzi