Abstract: A chip with flexible pad sequence manipulation is provided. The chip can be a memory controller, and includes a hub unit. The hub unit, formed by a gate array, is placed in a hub region predetermined during placing and routing procedures, and is capable of supporting re-placing and re-routing for changing interior interconnections and a pad sequence of the chip.

Abstract: The invention is directed to a memory controller and an associated signal generating method. By appropriately arranging a sequence according to which command signals are generated and expanding a latching interval of a part of address signals, not only the memory controller is enabled to control the DDR memory modules in a functional manner to further overcome issues of conventionally small latching intervals, but also system stability and access performance are reinforced as the memory access clock speed continue to increase.

Abstract: A memory controller is connected to a double-data-rate dynamic random access memory (DDR DRAM) and an accessing unit. The memory controller includes: a processing unit, configured to receive a system address generated by the accessing unit; and a mapping unit, located in the processing unit, configured to convert the system address to a memory address and transmitting the memory address to the DDR DRAM. When a burst length of the DDR DRAM is L and L=2x (where L and x are positive integers), an (x+1)th bit of the memory address from a least significant bit (LSB) is included in a bank group address of the memory address.

Abstract: A display controller, video signal transmitting method and system thereof are provided. The display controller includes a processing circuit; a transmitting channel, coupled to the processing circuit; a receiving channel, coupled to the processing circuit; and a clock generator, that generates an internal clock signal and an external clock signal. Upon receiving a video signal, the processing circuit processes a first partial pixel data of the video signal to output a first display control signal. The transmitting channel converts a second partial pixel data of the video signal to a partial video signal having a multiple data rate according to the internal clock signal to be outputted.

Abstract: An optical drive servo control system comprises: an optical pickup, for accessing an optical disc and generating an optical signal; a spindle motor, for rotating the optical disc and outputting a FG signal and a spindle motor synchronous signal; a frequency-multiplied FG signal generator, for generating an actual frequency-multiplied FG signal after receiving the FG signal, the spindle motor synchronous signal, a reference clock signal, and a frequency-multiplier value; and, a servo control unit, for controlling the spindle motor and the optical pickup, and compensating a run-out error of the optical disc according to the actual frequency-multiplied FG signal; wherein the frequency-multiplied FG signal generator calculates an ideal frequency-multiplied FG signal according to the reference clock signal and the frequency-multiplier value, and a positioning error between the ideal frequency-multiplied FG signal and the actual frequency-multiplied FG signal is less than half of a period of the reference clock sig

Abstract: An optical drive servo control system comprises: an optical pickup, for accessing an optical disc and generating an optical signal; a spindle motor, for rotating the optical disc and outputting a FG signal and a spindle motor synchronous signal; a frequency-multiplied FG signal generator, for generating an actual frequency-multiplied FG signal after receiving the FG signal, the spindle motor synchronous signal, a reference clock signal, and a frequency-multiplier value; and, a servo control unit, for controlling the spindle motor and the optical pickup, and compensating a run-out error of the optical disc according to the actual frequency-multiplied FG signal; wherein the frequency-multiplied FG signal generator calculates an ideal frequency-multiplied FG signal according to the reference clock signal and the frequency-multiplier value, and a positioning error between the ideal frequency-multiplied FG signal and the actual frequency-multiplied FG signal is less than half of a period of the reference clock sig