Patents by Inventor Chen-Ping Chen

Chen-Ping Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120049294
    Abstract: A device includes a plurality of intra-device insulation regions having a first height; and a plurality of semiconductor fins horizontally spaced apart from each other by the plurality of intra-device insulation regions. A portion of the plurality of semiconductor fins is disposed above the plurality of intra-device insulation regions. The device further includes a first inter-device insulation region and a second inter-device insulation region with the plurality of semiconductor fins disposed therebetween. The first and the second inter-device insulation regions have a second height greater than the first height.
    Type: Application
    Filed: September 1, 2010
    Publication date: March 1, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Ping Chen, Hui-Min Lin, Ming-Jie Huang, Tung Ying Lee
  • Publication number: 20120021607
    Abstract: An embodiment of the disclosure includes a method of pitch reduction. A substrate is provided. A first material layer is formed over the substrate. A second material layer is formed on the first material layer. A hardmask layer is formed on the second material layer. A first imaging layer is formed on the hardmask layer. The first imaging layer is patterned to form a plurality of first features over the hardmask layer. The hardmask layer is etched utilizing the first imaging layer as a mask to form the first features in the hardmask layer. The first imaging layer is removed to expose the etched hardmask layer and a portion of a top surface of the second material layer. A second imaging layer is formed and the process is repeated, such that first and second features are alternating with a pitch substantially half the original pitch.
    Type: Application
    Filed: July 23, 2010
    Publication date: January 26, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Jie HUANG, Chen-Ping CHEN
  • Patent number: 8048764
    Abstract: A method of forming a hardmask for defining shallow trench isolation regions in a semiconductor substrate layer includes the steps of: depositing a hardmask layer over the semiconductor substrate layer; depositing and patterning a first photoresist layer over the hardmask layer; etching the hardmask layer after patterning the first photoresist layer to form an interim hardmask layer having at least one line feature; depositing and patterning a second photoresist layer over the interim hardmask layer; and forming a hardmask, the forming step including etching the interim hardmask layer after patterning the second photoresist layer to define a line end of the at least one line feature.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: November 1, 2011
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Jie Huang, Chen-Ping Chen, Tung-Ying Lee
  • Publication number: 20110084355
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, an isolation feature disposed on the substrate, and an active area disposed adjacent the isolation feature. The isolation feature may be a shallow trench isolation feature. The STI feature has a first width at the top of the feature and a second width at the bottom of the feature. The first width is less than the second width. Methods of fabricating a semiconductor device is also provided. A method includes forming shallow trench isolation features and then growing an epitaxial layer adjacent the STI features to form an active region.
    Type: Application
    Filed: October 9, 2009
    Publication date: April 14, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsien-Hsin Lin, Bor Chiuan Hsieh, Chen-Ping Chen
  • Publication number: 20110076832
    Abstract: A method of forming a hardmask for defining shallow trench isolation regions in a semiconductor substrate layer includes the steps of: depositing a hardmask layer over the semiconductor substrate layer; depositing and patterning a first photoresist layer over the hardmask layer; etching the hardmask layer after patterning the first photoresist layer to form an interim hardmask layer having at least one line feature; depositing and patterning a second photoresist layer over the interim hardmask layer; and forming a hardmask, the forming step including etching the interim hardmask layer after patterning the second photoresist layer to define a line end of the at least one line feature.
    Type: Application
    Filed: September 30, 2009
    Publication date: March 31, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Jie HUANG, Chen-Ping CHEN, Tung-Ying LEE