Patents by Inventor Chen-Shien Chen

Chen-Shien Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10985114
    Abstract: A system and method for preventing cracks in a passivation layer is provided. In an embodiment a contact pad has a first diameter and an opening through the passivation layer has a second diameter, wherein the first diameter is greater than the second diameter by a first distance of about 10 ?m. In another embodiment, an underbump metallization is formed through the opening, and the underbump metallization has a third diameter that is greater than the first diameter by a second distance of about 5 ?m. In yet another embodiment, a sum of the first distance and the second distance is greater than about 15 ?m. In another embodiment the underbump metallization has a first dimension that is less than a dimension of the contact pad and a second dimension that is greater than a dimension of the contact pad.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: April 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Feng Chen, Yen-Liang Lin, Tin-Hao Kuo, Sheng-Yu Wu, Chen-Shien Chen
  • Patent number: 10978433
    Abstract: A package for a use in a package-on-package (PoP) device and a method of forming is provided. The package includes a substrate, a polymer layer formed on the substrate, a first via formed in the polymer layer, and a material disposed in the first via to form a first passive device. The material may be a high dielectric constant dielectric material in order to form a capacitor or a resistive material to form a resistor.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: April 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Ching-Wen Hsiao, Chen-Shien Chen
  • Patent number: 10964610
    Abstract: Embodiments of mechanisms for testing a die package with multiple packaged dies on a package substrate use an interconnect substrate to provide electrical connections between dies and the package substrate and to provide probing structures (or pads). Testing structures, including daisy-chain structures, with metal lines to connect bonding structures connected to signals, power source, and/or grounding structures are connected to probing structures on the interconnect substrate. The testing structures enable determining the quality of bonding and/or functionalities of packaged dies bonded. After electrical testing is completed, the metal lines connecting the probing structures and the bonding structures are severed to allow proper function of devices in the die package. The mechanisms for forming test structures with probing pads on interconnect substrate and severing connecting metal lines after testing could reduce manufacturing cost.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hua Chen, Chen-Shien Chen, Ching-Wen Hsiao
  • Publication number: 20210074673
    Abstract: Disclosed herein is a bump-on-trace interconnect with a wetted trace sidewall and a method for fabricating the same. A first substrate having conductive bump with solder applied is mounted to a second substrate with a trace disposed thereon by reflowing the solder on the bump so that the solder wets at least one sidewall of the trace, with the solder optionally wetting between at least half and all of the height of the trace sidewall. A plurality of traces and bumps may also be disposed on the first substrate and second substrate with a bump pitch of less than about 100 ?m, and volume of solder for application to the bump calculated based on at least one of a joint gap distance, desired solder joint width, predetermined solder joint separation, bump geometry, trace geometry, minimum trace sidewall wetting region height and trace separation distance.
    Type: Application
    Filed: November 23, 2020
    Publication date: March 11, 2021
    Inventors: Chen-Hua Yu, Chen-Shien Chen
  • Publication number: 20210066181
    Abstract: A method for forming a chip package structure is provided. The method includes providing a wiring substrate. The method includes sequentially forming a nickel-containing layer and a gold-containing layer over the first pad. The method includes forming a conductive protection layer covering the gold-containing layer over the nickel-containing layer. The method includes bonding a chip to the wiring substrate through a conductive bump and a flux layer surrounding the conductive bump. The conductive bump is between the second pad and the chip. The method includes removing the flux layer while the conductive protection layer covers the nickel-containing layer.
    Type: Application
    Filed: June 5, 2020
    Publication date: March 4, 2021
    Inventors: Yu-Huan CHEN, Kuo-Ching HSU, Chen-Shien CHEN
  • Publication number: 20210035938
    Abstract: The present disclosure relates to an integrated chip structure having a first copper pillar disposed over a metal pad of an interposer substrate. The first copper pillar has a sidewall defining a recess. A nickel layer is disposed over the first copper pillar and a solder layer is disposed over the first copper pillar and the nickel layer. The solder layer continuously extends from directly over the first copper pillar to within the recess. A second copper layer is disposed between the solder layer and a second substrate.
    Type: Application
    Filed: October 21, 2020
    Publication date: February 4, 2021
    Inventors: Chih-Horng Chang, Tin-Hao Kuo, Chen-Shien Chen, Yen-Liang Lin
  • Publication number: 20210035937
    Abstract: A method for forming a package structure includes forming an under bump metallization (UBM) layer over a metal pad and forming a photoresist layer over the UBM layer. The method further includes patterning the photoresist layer to form an opening in the photoresist layer. The method also includes forming a first bump structure over the first portion of the UBM layer. The first bump structure includes a first barrier layer over a first pillar layer. The method includes placing a second bump structure over the first bump structure. The second bump structure includes a second barrier layer over a second pillar layer. The method further includes reflowing the first bump structure and the second bump structure to form a solder joint between a first inter intermetallic compound (IMC) and a second IMC.
    Type: Application
    Filed: October 16, 2020
    Publication date: February 4, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hung CHEN, Yu-Nu HSU, Chun-Chen LIU, Heng-Chi HUANG, Chien-Chen LI, Shih-Yen CHEN, Cheng-Nan HSIEH, Kuo-Chio LIU, Chen-Shien CHEN, Chin-Yu KU, Te-Hsun PANG, Yuan-Feng WU, Sen-Chi CHIANG
  • Publication number: 20210013158
    Abstract: A method for manufacturing a semiconductor package includes following operations. A die having a first surface and a second surface opposite to the first surface is provided. A polymeric film is disposed over the second surface of the die. An adhesive film is provided. The die and the polymeric film are attached to a carrier substrate through the adhesive film. The die, the polymeric film and the adhesive film are molded with a molding compound. The polymeric film is sandwiched between the die and the adhesive film upon attaching to the carrier substrate.
    Type: Application
    Filed: September 22, 2020
    Publication date: January 14, 2021
    Inventors: CHEN-SHIEN CHEN, MING-DA CHENG, MING-CHIH YEW, YU-TSE SU
  • Patent number: 10879228
    Abstract: A semiconductor package includes a package substrate. A redistribution structure is bonded to the package substrate. A bottommost surface of the redistribution structure is lower than a topmost surface of the package substrate. A conductive connector electrically couples the redistribution structure to the package substrate. The conductive connector physically contacts a sidewall of the redistribution structure. A first integrated circuit die is bonded to the redistribution structure through first bonding structures and is bonded to the package substrate through second bonding structures. The first bonding structures and the second bonding structures have different sizes.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hua Chen, Chen-Shien Chen, Ching-Wen Hsiao
  • Patent number: 10867976
    Abstract: An embodiment package includes a first package. The first package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and redistribution layers over the encapsulant and the first integrated circuit die. The package also includes a second package bonded to the first package by a plurality of functional connectors. The functional connectors and the redistribution layers electrically connect a second integrated circuit die of the second package to the first integrated circuit die. The package also includes a plurality of dummy connectors disposed between the first package and the second package. One end of each of the plurality of dummy connectors facing the first package is physically separated from the first package.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Shien Chen, Hsiu-Jen Lin, Ming-Chih Yew, Ming-Da Cheng, Yi-Jen Lai, Yu-Tse Su, Sey-Ping Sun, Yang-Che Chen
  • Patent number: 10867810
    Abstract: A method includes forming a plurality of vias in a dielectric layer and over a package substrate and forming a plurality of top pads over the dielectric layer, each of the plurality of top pads being connected to a respective via of the plurality of vias, wherein the plurality of top pads includes a first group, a second group, a third group and a fourth group, wherein the first group is separated from the fourth group by a first pad line, wherein the first group is separated from the second group by a second pad line, the first pad line comprising a plurality of first elongated pads, the second pad line comprising a plurality of second elongated pads, the second pad line being orthogonal to the first pad line.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Juin Liu, Chita Chuang, Yao-Chun Chuang, Ming Hung Tseng, Chen-Shien Chen
  • Patent number: 10868106
    Abstract: A method of manufacturing a semiconductor device and the semiconductor device are provided in which a plurality of layers with cobalt-zirconium-tantalum are formed over a semiconductor substrate, the plurality of layers are patterned, and multiple dielectric layers and conductive materials are deposited over the CZT material. Another layer of CZT material encapsulates the conductive material.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Li Huang, Chi-Cheng Chen, Hon-Lin Huang, Chien-Chih Chou, Chin-Yu Ku, Chen-Shien Chen
  • Patent number: 10861811
    Abstract: Connector structures and methods of forming the same are provided. A method includes forming a first patterned passivation layer on a workpiece, the first patterned passivation layer having a first opening exposing a conductive feature of the workpiece. A seed layer is formed over the first patterned passivation layer and in the first opening. A patterned mask layer is formed over the seed layer, the patterned mask layer having a second opening exposing the seed layer, the second opening overlapping with the first opening. A connector is formed in the second opening. The patterned mask layer is partially removed, an unremoved portion of the patterned mask layer remaining in the first opening. The seed layer is patterned using the unremoved portion of the patterned mask layer as a mask.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Chen-Shien Chen, Sheng-Yu Wu, Mirng-Ji Lii, Chita Chuang
  • Publication number: 20200381293
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first conductive line over a substrate. The semiconductor device structure includes a first protection cap over the first conductive line. The semiconductor device structure includes a first photosensitive dielectric layer over the substrate, the first conductive line, and the first protection cap. The semiconductor device structure includes a conductive via structure passing through the first photosensitive dielectric layer and connected to the first protection cap. The semiconductor device structure includes a second conductive line over the conductive via structure and the first photosensitive dielectric layer. The semiconductor device structure includes a second protection cap over the second conductive line. The semiconductor device structure includes a second photosensitive dielectric layer over the first photosensitive dielectric layer, the second conductive line, and the second protection cap.
    Type: Application
    Filed: August 14, 2020
    Publication date: December 3, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ting-Li YANG, Wei-Li HUANG, Sheng-Pin YANG, Chi-Cheng CHEN, Hon-Lin HUANG, Chin-Yu KU, Chen-Shien CHEN
  • Patent number: 10854577
    Abstract: A package includes package includes a first package component including a first plurality of electrical connectors at a top surface of the first package component, and a second plurality of electrical connectors longer than the first plurality of electrical connectors at the top surface of the first package component. A first device die is over the first package component and bonded to the first plurality of electrical connectors. A second package component is overlying the first package component and the first device die. The second package component includes a third plurality of electrical connectors at a bottom surface of the second package component. The third plurality of electrical connectors is bonded to the second plurality of electrical connectors. A fourth plurality of electrical connectors is at a bottom surface of the second package. The second and the fourth plurality of electrical connectors comprise non-solder metallic materials.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chen-Shien Chen, Shou-Cheng Hu
  • Patent number: 10847493
    Abstract: Disclosed herein is a bump-on-trace interconnect with a wetted trace sidewall and a method for fabricating the same. A first substrate having conductive bump with solder applied is mounted to a second substrate with a trace disposed thereon by reflowing the solder on the bump so that the solder wets at least one sidewall of the trace, with the solder optionally wetting between at least half and all of the height of the trace sidewall. A plurality of traces and bumps may also be disposed on the first substrate and second substrate with a bump pitch of less than about 100 ?m, and volume of solder for application to the bump calculated based on at least one of a joint gap distance, desired solder joint width, predetermined solder joint separation, bump geometry, trace geometry, minimum trace sidewall wetting region height and trace separation distance.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: November 24, 2020
    Assignee: Taiwan Semiconductor Manufacturing, Ltd.
    Inventors: Chen-Hua Yu, Chen-Shien Chen
  • Patent number: 10833033
    Abstract: The present disclosure, in some embodiments, relates to a bump structure. The bump structure includes a conductive layer and a solder layer. The solder layer is disposed vertically below and laterally between portions of the conductive layer along a cross-section. The conductive layer is continuous between the portions.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: November 10, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Horng Chang, Tin-Hao Kuo, Chen-Shien Chen, Yen-Liang Lin
  • Publication number: 20200350782
    Abstract: Wireless charging devices, methods of manufacture thereof, and methods of charging electronic devices are disclosed. In some embodiments, a wireless charging device includes a controller, a molding material disposed around the controller, and an interconnect structure disposed over the molding material and coupled to the controller. The wireless charging device includes a wireless charging coil coupled to the controller. The wireless charging coil comprises a first portion disposed in the interconnect structure and a second portion disposed in the molding material. The wireless charging coil is adapted to provide an inductance to charge an electronic device.
    Type: Application
    Filed: July 20, 2020
    Publication date: November 5, 2020
    Inventors: Chen-Hua Yu, Chita Chuang, Chen-Shien Chen, Ming Hung Tseng, Sen-Kuei Hsu, Yu-Feng Chen, Yen-Liang Lin
  • Publication number: 20200350395
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a magnetic element over the semiconductor substrate. The magnetic element has a first edge. The semiconductor device structure also includes an adhesive element between the magnetic element and the semiconductor substrate, and the adhesive element has a second edge. The semiconductor device structure further includes an isolation element extending across the magnetic element. The isolation element partially covers a top surface of the magnetic element and partially covers sidewall surfaces of the magnetic element. The isolation element has a third edge, and the second edge is closer to the third edge than the first edge. In addition, the semiconductor device structure includes a conductive line over the isolation element.
    Type: Application
    Filed: July 20, 2020
    Publication date: November 5, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Cheng CHEN, Wei-Li HUANG, Chien-Chih KUO, Hon-Lin HUANG, Chin-Yu KU, Chen-Shien CHEN
  • Publication number: 20200343162
    Abstract: A semiconductor device includes a first conductive layer, an organic layer and a silicon layer. The first conductive layer includes a first surface. The organic layer is disposed over the first surface of the first conductive layer. The silicon layer is disposed over the organic layer and extended onto and in contact with the first surface of the first conductive layer.
    Type: Application
    Filed: July 9, 2020
    Publication date: October 29, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Lung Yang, Chih-Hung Su, Chen-Shien Chen, Hon-Lin Huang, Kun-Ming Tsai, Wei-Je Lin