Patents by Inventor Chen Tseng
Chen Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12262057Abstract: A method for compressing images based on joint photographic experts group (JPEG) standard includes: compressing data of one or more first image blocks with a first compression level to produce compression data of the one or more first image blocks; adjusting the first compression level to obtain a second compression level according to at least one of a data size-related index regarding the compression data of the one or more first image blocks or a transmission-related index regarding transmission of the compression data of the one or more first image blocks; and compressing data of a second image block with the second compression level.Type: GrantFiled: March 22, 2022Date of Patent: March 25, 2025Assignee: Realtek Semiconductor Corp.Inventors: Hsu-Jung Tung, Chi-Wang Chai, Weimin Zeng, Yi-Chen Tseng
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Publication number: 20250032621Abstract: A drug conjugate includes a structure shown by the following formula: Z-(linker-[R]m)n. In the formula, Z is a drug compound, R is a sugar, and m and n are independently an integer from 1 to 6. The drug compound Z is a hepatitis virus targeting drug, a hepatitis B virus (HBV) drug, an inhibitor of apoptosis protein (IAP) antagonist, a multidrug resistance (MDR) inhibitor, or analogues, precursors, prodrugs, derivatives thereof.Type: ApplicationFiled: May 30, 2024Publication date: January 30, 2025Applicant: SeeCure Taiwan Co., Ltd.Inventors: Wuu-Jyh Lin, Min-Ching Chung, Chi-Shiang Ke, Ya-Chen Tseng, Chin-Yu Liang, Yen-Chun Lee, Hsin-Jou Li, Tai-Yun Huang, Nai-Chen Hsueh, Yan-Feng Jiang
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Publication number: 20240421005Abstract: An exemplary method includes, capturing, during a semiconductor fabrication process performed using a semiconductor processing device including a liquid distribution component configured to dispense a liquid flowing with an intact curtain profile, first images of a view of a chamber of the semiconductor processing device. The method includes determining curtain profile classifications of the first images. A curtain profile classification of the curtain profile classifications indicates a first value indicating that an image exhibits the liquid flowing with the intact curtain profile, or a second value indicating that the image does not exhibit the liquid flowing with the intact curtain profile. The method includes determining a plurality of groups of images based upon an order of the first images and the curtain profile classifications of the first images.Type: ApplicationFiled: June 13, 2023Publication date: December 19, 2024Inventors: Chen TSENG, Yang-Shu LIN
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Publication number: 20240387310Abstract: A package and a method forming the same are provided. The package includes an integrated circuit die. A sidewall of the integrated circuit die has a first facet and a second facet. The first facet and the second facet have different slopes. The package includes an encapsulant surrounding the integrated circuit die and in physical contact with the first facet and the second facet and an insulating layer over the integrated circuit die and the encapsulant. An upper surface of the integrated circuit die is lower than an upper surface of the encapsulant. A sidewall of the insulating layer is substantially coplanar with the first facet.Type: ApplicationFiled: July 30, 2024Publication date: November 21, 2024Inventors: Ting-Chen Tseng, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
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Patent number: 12094765Abstract: In an embodiment, a method includes: dispensing a first dielectric layer around and on a first metallization pattern, the first dielectric layer including a photoinsensitive molding compound; planarizing the first dielectric layer such that surfaces of the first dielectric layer and the first metallization pattern are planar; forming a second metallization pattern on the first dielectric layer and the first metallization pattern; dispensing a second dielectric layer around the second metallization pattern and on the first dielectric layer, the second dielectric layer including a photosensitive molding compound; patterning the second dielectric layer with openings exposing portions of the second metallization pattern; and forming a third metallization pattern on the second dielectric layer and in the openings extending through the second dielectric layer, the third metallization pattern coupled to the portions of the second metallization pattern exposed by the openings.Type: GrantFiled: January 17, 2022Date of Patent: September 17, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ting-Chen Tseng, Sih-Hao Liao, Po-Han Wang, Yu-Hsiang Hu, Hung-Jui Kuo
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Publication number: 20240297053Abstract: A method includes attaching an integrated circuit die adjacent to a first substrate, the integrated circuit die comprising: an active device in a second substrate; a pad adjacent to the second substrate; and a first dielectric layer adjacent to the second substrate, the first dielectric layer comprising a polyimide with an ester group; forming an encapsulant around the integrated circuit die; and removing the first dielectric layer.Type: ApplicationFiled: May 6, 2024Publication date: September 5, 2024Inventors: Ting-Chen Tseng, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
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Patent number: 12041742Abstract: An apparatus simulates cable routing for determining signal integrity between electronic components within a computer chassis. The apparatus includes a base plate simulating a computer chassis base. The base plate includes a top surface. The apparatus further includes a plurality of reconfigurable mounting fixtures, each allowing temporary mounting of a printed circuit board assembly (PCBA) to a respective reconfigurable mounting fixture. Each of the plurality of reconfigurable mounting fixtures is temporarily mountable anywhere on the top surface of the base plate. The apparatus further includes a cable having a first end connector that allows a connection to a first PCBA, and a second end connector that allows a connection to a second PCBA.Type: GrantFiled: October 19, 2020Date of Patent: July 16, 2024Assignee: QUANTA COMPUTER INC.Inventors: Yaw-Tzorng Tsorng, Chen-Chien Kuo, Chen Tseng
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Patent number: 12009226Abstract: A method includes attaching an integrated circuit die adjacent to a first substrate, the integrated circuit die comprising: an active device in a second substrate; a pad adjacent to the second substrate; and a first dielectric layer adjacent to the second substrate, the first dielectric layer comprising a polyimide with an ester group; forming an encapsulant around the integrated circuit die; and removing the first dielectric layer.Type: GrantFiled: August 27, 2021Date of Patent: June 11, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ting-Chen Tseng, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
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Publication number: 20240181257Abstract: The present disclosure provides a medical device (100) for electrical stimulation. The medical device (100) includes electric circuitry configured to perform active charge compensation, said electric circuitry being connectable to at least one electrode arrangement (102) for electrical stimulation. The electric circuitry includes monitoring means configured to monitor at least one voltage associated with a stimulation network (108, 116); at least one variable resistive element configured to provide an voltage drop used in the active charge compensation: and adjustment means configured to dynamically adjust a resistance value of the at least one variable resistive element during the active charge compensation based on the at least one monitored voltage, wherein the adjustment means (202) is a finite state machine for neurostimulation.Type: ApplicationFiled: March 14, 2022Publication date: June 6, 2024Inventors: John Grimes, Vighnesh Rudra Das, Marcelo Baru, Brad McMillan, Linh Thuy Nguyen, Richard Yi Chen Tseng, David Genzer, Ashok Nedungadi
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Publication number: 20240118202Abstract: A rapid fresh digital-pathology (RFP) method for assessing an excised unfixed biological specimen stained with hematoxylin (H) or eosin (E) or both hematoxylin and eosin (HE) staining dyes. The RFP method is assisted by a rapid tissue staining (RTS) procedure which is performed on the excised unfixed biological specimen, involving a short fixation; an H-staining; a rinsing; a bluing; an E-staining; a rinsing; and finally, a covering of a stained specimen with a coverslip. The RFP method is further assisted by a multimodal nonlinear optical laser-raster-scanning approach to provide with a nonlinear multi-harmonic generation and/or a nonlinear multi-photon excitation fluorescence signal(s) for multichannel digitization and real-time digital display of H- or E- or HE-specific histopathological features while providing a centimeter-scale imaging area, a submicron digital resolution, and a sustained effective data throughput of at least 500 Megabits per second (Mbps).Type: ApplicationFiled: October 11, 2022Publication date: April 11, 2024Inventors: Chi-Kuang Sun, Bhaskar Jyoti Borah, Yao-Chen Tseng
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Publication number: 20240048740Abstract: An image processing device includes an image encoder, a memory and an image decoder. The image encoder receives an input image frame, retrieves luminance information and chrominance information from the input image frame, respectively, encodes the luminance information to generate an encoded luminance frame, and encodes the chrominance information to generate an encoded chrominance frame. The memory includes a first memory portion, a second memory portion and a third memory portion. The first memory portion stores the encoded luminance frame, and the second memory portion or the third memory portion stores the encoded chrominance frame. The image decoder reads the encoded luminance frame from the first memory portion to perform decoding, and reads the encoded chrominance frame from the second memory portion or the third memory portion for decoding.Type: ApplicationFiled: April 17, 2023Publication date: February 8, 2024Applicant: Realtek Semiconductor Corp.Inventors: Yi-Chen Tseng, Po-Hsien Wu
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Publication number: 20240048734Abstract: An image processing method includes receiving an image frame, retrieving luminance information and chrominance information from the image frame, respectively, encoding the luminance information to generate an encoded luminance frame, encoding the chrominance information to generate an encoded chrominance frame, writing the encoded luminance frame to a first memory portion of a memory, and writing the encoded chrominance frame to a second memory portion of the memory. The image processing method further includes reading the encoded luminance frame from the first memory portion and decoding the encoded luminance frame to generate decoded luminance information, and reading the encoded chrominance frame from the second memory portion and decoding the encoded chrominance frame to generate decoded chrominance information.Type: ApplicationFiled: April 17, 2023Publication date: February 8, 2024Applicant: Realtek Semiconductor Corp.Inventors: Po-Hsien Wu, Yi-Chen Tseng
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Patent number: 11880140Abstract: The present disclosure, in some embodiments, relates to a method of developing a photosensitive material. The method includes forming a photosensitive material over a substrate. The photosensitive material is exposed to electromagnetic radiation focused at a plurality of different heights over the substrate. The plurality of different heights are vertically separated from one another and are disposed within the photosensitive material along a vertical path that extends in a direction perpendicular to an upper surface of the photosensitive material. The photosensitive material is developed to remove a soluble region.Type: GrantFiled: November 15, 2022Date of Patent: January 23, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jun-Yih Yu, De-Fang Huang, De-Chen Tseng, Jia-Feng Chang, Li-Fang Hsu
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Patent number: 11862594Abstract: A package structure includes a semiconductor die, conductive pillars, an insulating encapsulation, a redistribution circuit structure, and a solder resist layer. The conductive pillars are arranged aside of the semiconductor die. The insulating encapsulation encapsulates the semiconductor die and the conductive pillars, and the insulating encapsulation has a first surface and a second surface opposite to the first surface. The redistribution circuit structure is located on the first surface of the insulating encapsulation. The solder resist layer is located on the second surface of the insulating encapsulation, wherein a material of the solder resist layer includes a filler.Type: GrantFiled: December 18, 2019Date of Patent: January 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ting-Chen Tseng, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao
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Publication number: 20230418560Abstract: The present invention discloses a computation circuit. Each of a first and a second term computation circuits includes higher bit computation circuits, a lowest bit computation circuit and a first adder. Each of the higher bit computation circuits left-shifts a multiplier, outputs the effective shifted multiplier having a sign determined and further performs left-shifts without performing 2's complement computation to generate a higher bit computation result. The lowest bit computation circuit outputs the effective multiplier having the sign determined to generate a lowest bit computation result. The first adder adds the bit computation results to generate a term computation result. The third term computation circuit outputs an effective addend having the sign determined and adds the addend to the summation of a number of 2's complement to generate a third term computation result. The second adder adds the term computation results and the third term computation result to generate a total computation result.Type: ApplicationFiled: June 20, 2023Publication date: December 28, 2023Inventors: SZU-CHUN CHANG, YI-CHEN TSENG
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Patent number: 11854927Abstract: A package and a method forming the same are provided. The package includes an integrated circuit die. A sidewall of the integrated circuit die has a first facet and a second facet. The first facet and the second facet have different slopes. The package includes an encapsulant surrounding the integrated circuit die and in physical contact with the first facet and the second facet and an insulating layer over the integrated circuit die and the encapsulant. An upper surface of the integrated circuit die is lower than an upper surface of the encapsulant. A sidewall of the insulating layer is substantially coplanar with the first facet.Type: GrantFiled: May 28, 2021Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ting-Chen Tseng, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
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Publication number: 20230386906Abstract: In an embodiment, a method includes: dispensing a first dielectric layer around and on a first metallization pattern, the first dielectric layer including a photoinsensitive molding compound; planarizing the first dielectric layer such that surfaces of the first dielectric layer and the first metallization pattern are planar; forming a second metallization pattern on the first dielectric layer and the first metallization pattern; dispensing a second dielectric layer around the second metallization pattern and on the first dielectric layer, the second dielectric layer including a photosensitive molding compound; patterning the second dielectric layer with openings exposing portions of the second metallization pattern; and forming a third metallization pattern on the second dielectric layer and in the openings extending through the second dielectric layer, the third metallization pattern coupled to the portions of the second metallization pattern exposed by the openings.Type: ApplicationFiled: August 9, 2023Publication date: November 30, 2023Inventors: Ting-Chen Tseng, Sih-Hao Liao, Po-Han Wang, Yu-Hsiang Hu, Hung-Jui Kuo
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Publication number: 20230386955Abstract: A package and a method forming the same are provided. The package includes an integrated circuit die. A sidewall of the integrated circuit die has a first facet and a second facet. The first facet and the second facet have different slopes. The package includes an encapsulant surrounding the integrated circuit die and in physical contact with the first facet and the second facet and an insulating layer over the integrated circuit die and the encapsulant. An upper surface of the integrated circuit die is lower than an upper surface of the encapsulant. A sidewall of the insulating layer is substantially coplanar with the first facet.Type: ApplicationFiled: August 10, 2023Publication date: November 30, 2023Inventors: Ting-Chen Tseng, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
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Publication number: 20230308687Abstract: A method for compressing images based on joint photographic experts group (JPEG) standard includes: compressing data of one or more first image blocks with a first compression level to produce compression data of the one or more first image blocks; adjusting the first compression level to obtain a second compression level according to at least one of a data size-related index regarding the compression data of the one or more first image blocks or a transmission-related index regarding transmission of the compression data of the one or more first image blocks; and compressing data of a second image block with the second compression level.Type: ApplicationFiled: March 22, 2022Publication date: September 28, 2023Applicant: Realtek Semiconductor Corp.Inventors: Hsu-Jung Tung, Chi-Wang Chai, Weimin Zeng, Yi-Chen Tseng
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Publication number: 20230282558Abstract: A package structure includes a first redistribution layer, a semiconductor die and a second redistribution layer. The first redistribution layer includes a first dielectric layer, first conductive elements, second conductive elements, a top dielectric layer and an auxiliary dielectric portion. The first conductive elements and the second conductive elements are disposed on the first dielectric layer with a first pattern density and a second pattern density respectively. The top dielectric layer is disposed on the first dielectric layer and covering a top surface of the second conductive elements. The auxiliary dielectric portion is disposed in between the first dielectric layer and the top dielectric layer, and covering a top surface of the first conductive elements. The semiconductor die is disposed on the first redistribution layer. The second redistribution layer is disposed on the semiconductor die, and electrically connected to the semiconductor die and the first redistribution layer.Type: ApplicationFiled: March 1, 2022Publication date: September 7, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Han Wang, Sih-Hao Liao, Wei-Chih Chen, Hung-Chun Cho, Ting-Chen Tseng, Yu-Hsiang Hu, Hung-Jui Kuo