Patents by Inventor Chen-Wei Wu

Chen-Wei Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160181910
    Abstract: A driving circuit includes: a switching element having a first terminal to receive an input voltage, and a second terminal; an inductor coupled to the second terminal of the switching element; a switch and a current sensing element coupled in series to the second terminal of the switching element; and a control module compensating a voltage sensed by the current sensing element based on at least one of the input voltage and an output voltage across the switching element and the inductor to generate a compensated signal, and switching the switch from an ON state to an OFF state when the compensated signal exceeds a reference threshold for a delay time.
    Type: Application
    Filed: December 23, 2014
    Publication date: June 23, 2016
    Inventors: CHEN-WEI WU, FENG-HSU LIN, YUAN-LUN CHANG
  • Patent number: 9236459
    Abstract: Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices are presented. An IGBT-ESD device includes a semiconductor substrate and patterned insulation regions disposed on the semiconductor substrate defining a first active region and a second active region. A high-V N-well is formed in the first active region of the semiconductor substrate. A P-body doped region is formed in the second active region of the semiconductor substrate, wherein the high-V N-well and the P-body doped region are separated with a predetermined distance exposing the semiconductor substrate. A P+ doped drain region is disposed in the high-V N-well. A P+ diffused region and an N+ doped source region are disposed in the P-body doped region. A gate structure is disposed on the semiconductor substrate with one end adjacent to the N+ doped source region and the other end extending over the insulation region.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: January 12, 2016
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Yeh-Ning Jou, Shang-Hui Tu, Jui-Chun Chang, Chen-Wei Wu
  • Patent number: 8759096
    Abstract: Disclosed is a microfluidic chip and method using the same. The microfluidic chip comprises a substrate having a surface, and at least a tissue culture area formed on the surface of the substrate. The tissue culture area has a microfluidic channel formed by a plurality of connected geometrical structures (nozzle-type channels) having a predetermined depth. The microfluidic channel has an inlet and an outlet, which are at two ends of the microfluidic channel, for medium inputting and outputting, respectively. Additionally, at least an air-exchange hole is formed on the bottom of the microfluidic channel. By using the microfluidic chip for tissue culture, lateral flow speed and stress can be decreased, so as to prolong survival time of tissues (e.g. liver tissues).
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: June 24, 2014
    Assignee: National Tsing Hua University
    Inventors: Chen-Wei Wu, Cheng-Hsien Liu, Chau-Ting Yeh, Hui-Ling Lin, Hsin-Yu Lai, Tzu-Chi Yu
  • Patent number: 8166756
    Abstract: A turbine intake pressure release structure to control pressure release between a throttle and a first turbine boosted pressure outlet includes a pressure release valve which has a first pressure orifice, a second pressure orifice and a housing chamber, at least one controller which has a pressure detection end and a driven portion and a switch duct which has a first end opening, a second end opening and a third end opening. The first end opening is connected to a third turbine boosted pressure outlet. The second end opening leads to the atmosphere. The third end opening is connected to the second pressure orifice. The driven portion runs through the switch duct to close the second end opening through the driven portion drive a membrane to a first position or closes the first end opening through the driven portion to drive the membrane to a second position.
    Type: Grant
    Filed: April 17, 2009
    Date of Patent: May 1, 2012
    Assignee: China Engine Corporation
    Inventors: Jung-Chun Chen, Chun-I Wu, Pai-Hsiu Lu, Chen-Wei Wu
  • Publication number: 20120001225
    Abstract: Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices are presented. An IGBT-ESD device includes a semiconductor substrate and patterned insulation regions disposed on the semiconductor substrate defining a first active region and a second active region. A high-V N-well is formed in the first active region of the semiconductor substrate. A P-body doped region is formed in the second active region of the semiconductor substrate, wherein the high-V N-well and the P-body doped region are separated with a predetermined distance exposing the semiconductor substrate. A P+ doped drain region is disposed in the high-V N-well. A P+ diffused region and an N+ doped source region are disposed in the P-body doped region. A gate structure is disposed on the semiconductor substrate with one end adjacent to the N+ doped source region and the other end extending over the insulation region.
    Type: Application
    Filed: September 14, 2011
    Publication date: January 5, 2012
    Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Yeh-Ning Jou, Shang-Hui Tu, Jui-Chun Chang, Chen-Wei Wu
  • Patent number: 8049307
    Abstract: Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices are presented. An IGBT-ESD device includes a semiconductor substrate and patterned insulation regions disposed on the semiconductor substrate defining a first active region and a second active region. A high-V N-well is formed in the first active region of the semiconductor substrate. A P-body doped region is formed in the second active region of the semiconductor substrate, wherein the high-V N-well and the P-body doped region are separated with a predetermined distance exposing the semiconductor substrate. A P+ doped drain region is disposed in the high-V N-well. A P+ diffused region and an N+ doped source region are disposed in the P-body doped region. A gate structure is disposed on the semiconductor substrate with one end adjacent to the N+ doped source region and the other end extending over the insulation region.
    Type: Grant
    Filed: January 23, 2009
    Date of Patent: November 1, 2011
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Yeh-Ning Jou, Shang-Hui Tu, Jui-Chun Chang, Chen-Wei Wu
  • Publication number: 20100263371
    Abstract: A turbine intake pressure release structure to control pressure release between a throttle and a first turbine boosted pressure outlet includes a pressure release valve which has a first pressure orifice, a second pressure orifice and a housing chamber, at least one controller which has a pressure detection end and a driven portion and a switch duct which has a first end opening, a second end opening and a third end opening. The first end opening is connected to a third turbine boosted pressure outlet. The second end opening leads to the atmosphere. The third end opening is connected to the second pressure orifice. The driven portion runs through the switch duct to close the second end opening through the driven portion drive a membrane to a first position or closes the first end opening through the driven portion to drive the membrane to a second position.
    Type: Application
    Filed: April 17, 2009
    Publication date: October 21, 2010
    Inventors: Jung-Chun Chen, Chun-I Wu, Pai-Hsiu Lu, Chen-Wei Wu
  • Publication number: 20100216244
    Abstract: Disclosed is a microfluidic chip and method using the same. The microfluidic chip comprises a substrate having a surface, and at least a tissue culture area formed on the surface of the substrate. The tissue culture area has a microfluidic channel formed by a plurality of connected geometrical structures (nozzle-type channels) having a predetermined depth. The microfluidic channel has an inlet and an outlet, which are at two ends of the microfluidic channel, for medium inputting and outputting, respectively. Additionally, at least an air-exchange hole is formed on the bottom of the microfluidic channel. By using the microfluidic chip for tissue culture, lateral flow speed and stress can be decreased, so as to prolong survival time of tissues (e.g. liver tissues).
    Type: Application
    Filed: May 7, 2010
    Publication date: August 26, 2010
    Applicant: NATIONAL TSING HUA UNIVERSITY
    Inventors: Chen-Wei Wu, Cheng-Hsien Liu, Chau-Ting Yeh, Hui-Ling Lin, Hsin-Yu Lai, Tzu-Chi Yu
  • Publication number: 20100187566
    Abstract: Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices are presented. An IGBT-ESD device includes a semiconductor substrate and patterned insulation regions disposed on the semiconductor substrate defining a first active region and a second active region. A high-V N-well is formed in the first active region of the semiconductor substrate. A P-body doped region is formed in the second active region of the semiconductor substrate, wherein the high-V N-well and the P-body doped region are separated with a predetermined distance exposing the semiconductor substrate. A P+ doped drain region is disposed in the high-V N-well. A P+ diffused region and an N+ doped source region are disposed in the P-body doped region. A gate structure is disposed on the semiconductor substrate with one end adjacent to the N+ doped source region and the other end extending over the insulation region.
    Type: Application
    Filed: January 23, 2009
    Publication date: July 29, 2010
    Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Yeh-Ning Jou, Shang-Hui Tu, Jui-Chun Chang, Chen-Wei Wu