Patents by Inventor Chen-Yi Lee

Chen-Yi Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260150642
    Abstract: The present disclosure describes a method for forming a nitrogen-rich protective layer within a low-k layer of a metallization layer to prevent damage to the low-k layer from subsequent processing operations. The method includes forming, on a substrate, a metallization layer having conductive structures in a low-k dielectric. The method further includes forming a capping layer on the conductive structures, where forming the capping layer includes exposing the metallization layer to a first plasma process to form a nitrogen-rich protective layer below a top surface of the low-k dielectric, releasing a precursor on the metallization layer to cover top surfaces of the conductive structures with precursor molecules, and treating the precursor molecules with a second plasma process to dissociate the precursor molecules and form the capping layer. Additionally, the method includes forming an etch stop layer to cover the capping layer and top surfaces of the low-k dielectric.
    Type: Application
    Filed: December 23, 2025
    Publication date: May 28, 2026
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Yi LEE, Chia-Lin Hsu
  • Publication number: 20260103764
    Abstract: A method for detecting multiple pathogens is provided. The method involves linking multiple pathogens to fluorophores and then obtaining emission spectra of the pathogens using a prism-based fluorescence imaging system. In one embodiment, emission spectra of the fluorophores are obtained using optical detection and at least one other aspect of the pathogens is obtained using a silicon chip.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 16, 2026
    Applicant: University of Cincinnati
    Inventors: Jiajie Diao, Chen-Yi Lee
  • Patent number: 12594555
    Abstract: Microfluidic chips, microfluidic processing systems, and microfluidic processing methods are provided. A microfluidic chip includes a top plate and a microelectrode dot array arranged under the top plate. The microelectrode dot array includes microelectrode devices connected in a series. Each microelectrode device includes a microfluidic electrode under the top plate, a multi-functional electrode under the microfluidic electrode, and a control circuit under the multi-functional electrode. Each control circuit includes a first storage circuit, a second storage circuit, a microfluidic control and location-sensing circuit, and a temperature and magnetic control circuit. Each first storage circuit reads in a sample operation configuration. Each second storage circuit reads in a magnetic field control configuration. Each microfluidic control and location-sensing circuit enters a sample control status corresponding to a sample operation configuration.
    Type: Grant
    Filed: March 15, 2023
    Date of Patent: April 7, 2026
    Assignee: National Yang Ming Chiao Tung University
    Inventors: Chen-Yi Lee, Yun-Sheng Chan
  • Publication number: 20260092244
    Abstract: A micro-groove structure for cell culture includes a micro-groove body and a a microstructure unit. The micro-groove body is formed with a microculture space which has an opening and which is defined by a space-defining wall. The microstructure unit is formed on the micro-groove body and is located in the microculture space. The microstructure unit has microstructures which protrude from the space-defining wall into the microculture space. The microstructures cooperatively define a concave surface which tapers in a direction away from the opening of the microculture space and which is used to support cells. A cell culture device includes a substrate and cell culture well units. The cell culture well units are disposed in the substrate. Each of the cell culture well units has a main well body and at least one the micro-groove structure.
    Type: Application
    Filed: September 23, 2025
    Publication date: April 2, 2026
    Inventors: I-Fang CHENG, Chen-Yi LEE, Jyun-Hong WANG, Pei-Mei LU, Yi-Ching CHIU, Chao-Hong CHEN, Meng-Yen TSAI
  • Patent number: 12538775
    Abstract: The present disclosure describes a method for forming a nitrogen-rich protective layer within a low-k layer of a metallization layer to prevent damage to the low-k layer from subsequent processing operations. The method includes forming, on a substrate, a metallization layer having conductive structures in a low-k dielectric. The method further includes forming a capping layer on the conductive structures, where forming the capping layer includes exposing the metallization layer to a first plasma process to form a nitrogen-rich protective layer below a top surface of the low-k dielectric, releasing a precursor on the metallization layer to cover top surfaces of the conductive structures with precursor molecules, and treating the precursor molecules with a second plasma process to dissociate the precursor molecules and form the capping layer. Additionally, the method includes forming an etch stop layer to cover the capping layer and top surfaces of the low-k dielectric.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: January 27, 2026
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Yi Lee, Chia-Lin Hsu
  • Publication number: 20260010047
    Abstract: The present inventive concept discloses a programmable dielectrophoretic semiconductor chip, which comprises a microelectrode. The microelectrode comprises: a surface; a top electrode provided close to the surface; a first logic circuit used to receive and store a pattern signal; and a second logic circuit is used to receive a first analog signal and a second analog signal which are input from an external part of the microelectrode, wherein the second logic circuit is used to choose the first analog signal or the second analog signal according to the pattern signal which is received by the first logic circuit, and a voltage of the top electrode changes with the first analog signal or the second analog signal. The semiconductor chip of the present inventive concept is capable to move or position a specific single particle. In addition, the present inventive concept further provides a packaging structure with semiconductor chip and a control system of the semiconductor chip.
    Type: Application
    Filed: July 3, 2024
    Publication date: January 8, 2026
    Inventors: Chen-Yi Lee, Wen-Yue Lin, Lin-Hung Lai
  • Patent number: 12519473
    Abstract: The present inventive concept provides a capacitance sensor array chip with programmable fusion pixels comprising: a programmable module for generating a choosing signal according to a first clock signal; a delay pulse module for generating a third clock signal according to a second clock signal and a sensing pulse signal; and multiple electrode array modules comprising a charging unit for generating a charging signal according to the sensing pulse signal; M×N electrode pixel units forming an array, wherein the electrode arrays chooses a certain pattern of the electrode units according to the choosing signal in orders and the certain pattern of the electrode units in the electrode array generates a sampling signal according to the charging signal; and a sampling unit for generating a sensing output signal according to the sampling signal and the third clock signal.
    Type: Grant
    Filed: May 20, 2024
    Date of Patent: January 6, 2026
    Assignee: National Yang Ming Chiao Tung University
    Inventors: Chen-Yi Lee, Lin-Hung Lai, Wen-Yue Lin
  • Publication number: 20250359348
    Abstract: A semiconductor ESD protection device includes a pair of source regions, a pair of gate structures, a drain region, a plurality of first conductive contacts, a plurality of second conductive contacts, a plurality of third conductive contacts, and a dummy structure. The pair of gate structures are disposed between the pair of source regions and extend along a direction. The drain region is disposed between the pair of gate structures. Each of the first conductive contacts is disposed on one of the pair of source regions and is arranged along the direction. Each of the plurality of second conductive contacts is disposed on one of the pair of gate structures. The plurality of third conductive contacts are disposed on the drain region and arranged along the direction. The dummy structure is disposed over the drain region and between the gate structures and between the third conductive contacts.
    Type: Application
    Filed: July 31, 2025
    Publication date: November 20, 2025
    Inventors: SHENG-FU HSU, CHEN-YI LEE, LIN-YU HUANG, SHIH-FAN CHEN
  • Publication number: 20250357930
    Abstract: The present inventive concept provides a capacitance sensor array chip with programmable fusion pixels comprising: a programmable module for generating a choosing signal according to a first clock signal; a delay pulse module for generating a third clock signal according to a second clock signal and a sensing pulse signal; and multiple electrode array modules comprising a charging unit for generating a charging signal according to the sensing pulse signal; M×N electrode pixel units forming an array, wherein the electrode arrays chooses a certain pattern of the electrode units according to the choosing signal in orders and the certain pattern of the electrode units in the electrode array generates a sampling signal according to the charging signal; and a sampling unit for generating a sensing output signal according to the sampling signal and the third clock signal.
    Type: Application
    Filed: May 20, 2024
    Publication date: November 20, 2025
    Inventors: Chen-Yi Lee, Lin-Hung Lai, Wen-Yue Lin
  • Patent number: 12446323
    Abstract: A semiconductor ESD protection device includes a pair of source regions, a pair of gate structures, a drain region, a plurality of first conductive contacts, a plurality of second conductive contacts, a plurality of third conductive contacts, and a dummy structure. The pair of gate structures are disposed between the pair of source regions and extend along a direction. The drain region is disposed between the pair of gate structures. Each of the first conductive contacts is disposed on one of the pair of source regions and is arranged along the direction. Each of the plurality of second conductive contacts is disposed on one of the pair of gate structures. The plurality of third conductive contacts are disposed on the drain region and arranged along the direction. The dummy structure is disposed over the drain region and between the gate structures and between the third conductive contacts.
    Type: Grant
    Filed: January 9, 2023
    Date of Patent: October 14, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Sheng-Fu Hsu, Chen-Yi Lee, Lin-Yu Huang, Shih-Fan Chen
  • Publication number: 20250283151
    Abstract: Disclosed herein are methods for nuclear extraction and amplification using a bio-field programmable gate array. The method includes disposing a mixed droplet including one or more target nucleic acids adsorbed to magnetic beads on a microelectrode array including microelectrodes operable to form one or more actuated patterns. The method includes extracting the one or more target nucleic acids from the mixed droplet by attracting the one or more target nucleic acids using magnetic force generated by one or more coils under the microelectrodes, and switching one or more of the microelectrodes corresponding to a disposal actuated pattern to move the mixed droplet to a disposal location. The method includes merging the one or more target nucleic acids and an amplifying droplet to form a pre-amplifying droplet, heating the pre-amplifying droplet under a programmed temperature scheme to generate an amplified droplet, and visualizing the amplified droplet.
    Type: Application
    Filed: May 2, 2023
    Publication date: September 11, 2025
    Applicants: University of Cincinnati, National Yang Ming Chiao Tung University
    Inventors: Jiajie Diao, Chen-Yi Lee
  • Patent number: 12350682
    Abstract: A microelectrode device, microfluidic chip, and microfluidic examination method are provided. The microfluidic chip includes a top plate and a microelectrode dot array having several microelectrode devices. Each microelectrode device includes a microfluidic electrode, heating electrode, and control circuit. The control circuit includes a microfluidic control and location sensing circuit, storage circuit, and temperature control circuit. The microfluidic control and location sensing circuit moves a sample within an enabling period of a microfluidic control signal and detects a capacitance value between the microfluidic electrode and the top plate within an enabling period of a location control signal. The storage circuit outputs the capacitance value, reads in the sample operation setup, and reads in the heating control setup within different enabling periods of the clock.
    Type: Grant
    Filed: December 2, 2021
    Date of Patent: July 8, 2025
    Assignee: National Yang Ming Chiao Tung University
    Inventors: Chen-Yi Lee, Yun-Sheng Chan
  • Patent number: 12246317
    Abstract: A microfluidic test system and method are provided. The microfluidic test system includes a control apparatus and a microfluidic chip. The control apparatus stores a test protocol of a biomedical test. The microfluidic chip includes a top plate and a microelectrode dot array having a plurality of microelectrode devices connected in series. The control apparatus provides a location-sensing signal to the microfluidic chip so that each microelectrode device detects a capacitance value between the top plate and the corresponding microfluidic electrode accordingly. The control apparatus provides a clock signal to the microfluidic chip so that each microelectrode device outputs the corresponding capacitance value accordingly. The control apparatus determines the size and location of a test sample within the microfluidic chip, generates a control signal according to the test protocol, the size, and the location, and provides the control signal to the microfluidic chip.
    Type: Grant
    Filed: March 15, 2022
    Date of Patent: March 11, 2025
    Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventor: Chen-Yi Lee
  • Patent number: 12211174
    Abstract: A portable video display apparatus that adopts a L-layer processing architecture and performs the following operations for each layer of x1th layer to x2th layer: generating an optical flow map between a first and a second image frames, generating a primary rectified feature map according to a first feature map of the first image frame and the optical flow map, generating an advanced rectified feature map according to the optical flow map, the primary rectified feature map, and a second feature map of the second image frame, and generating a second feature map for the next layer according to the second feature map and the advanced rectified feature map. The portable video display apparatus generates an enlarged image frame by up-sampling the second image frame, generates a display image frame according to the second feature map at the x2+1th layer and the enlarged image frame and displays it.
    Type: Grant
    Filed: August 16, 2022
    Date of Patent: January 28, 2025
    Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Chen-Yi Lee, Eugene Eu Tzuan Lee
  • Patent number: 12208392
    Abstract: A particulate matter detection device and a detection method, in particular, a detection device and detection method based on a dielectrophoresis and electrical impedance measurement technology is provided, and more in particular, an electrical impedance detection device utilizing a microfluidic chip, and an application thereof for detecting target particles are provided. The device comprises a sample introducing part, a main channel (3), a dielectrophoresis electric field generating part, and an electrical impedance measurement part. By using the dielectrophoresis electric field generating part to selectively control target cells, detection or counting is performed on a sample flexibly and precisely without the use of labels and antibodies.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: January 28, 2025
    Assignee: SHANGHAI SGLCELL BIOTECH CO., LTD.
    Inventors: Chen-Yi Lee, Chao-Hong Chen, Jyun-Hong Wang, Yi Lu
  • Patent number: 12192661
    Abstract: An image sensor chip with depth information is provided. The image sensor chip includes an SPAD array, a time-to-digital converter module, a storage circuit, and a data processing circuit. The SPAD array includes a plurality of image sensor units, and each of the image sensor units includes a plurality of SPAD units and a decision circuit, wherein each of the SPAD units outputs a photon detection result within a scan period, and the decision circuit generates an image-sensing signal based on the photon detection results. The time-to-digital converter module generates a plurality of first time data in response to the image-sensing signals. The storage circuit stores the first time data temporarily. The data processing unit reads the first time data from the storage circuit and generates a plurality of second time data in response to the first time data.
    Type: Grant
    Filed: March 28, 2023
    Date of Patent: January 7, 2025
    Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Chen-Yi Lee, Hsi-Hao Huang, Tzu-Yun Huang
  • Publication number: 20240429310
    Abstract: A semiconductor device may include a electrostatic discharge (ESD) protection circuit and a high voltage ESD triggering circuit that is configured to trigger ESD protection for high voltage circuits of the semiconductor device. The high voltage ESD triggering circuit may be implemented by one or more of the example implementations of high voltage ESD triggering circuits described herein. The example implementations of high voltage ESD triggering circuits described herein are capable of handle high voltages of the high voltage circuits included in the semiconductor device. This reduces the likelihood of and/or prevents premature triggering of ESD protection during normal operation for these high voltage circuits, and enables the high voltage circuits to be protected from high voltage ESD events.
    Type: Application
    Filed: June 21, 2023
    Publication date: December 26, 2024
    Inventors: Sheng-Fu HSU, Shih-Fan CHEN, Chen-Yi LEE, Pin-Chen CHEN, Lin-Yu HUANG
  • Publication number: 20240351036
    Abstract: A microfluidic particle sorter includes a chip body and at least one sorting unit provided inside the chip body and including a microfluidic channel and at least one first DLD array. The microfluidic channel extends along a length direction, has an inlet and an outlet, and has a first side and a second side. The at least one first DLD array includes first DLD columns arranged along the length direction. The first DLD columns, from the inlet toward the outlet, are gradually shifted toward the second side such that two adjacent ones of the first DLD columns are offset from each other by a predetermined distance. Each of the first DLD columns has first split pillars. Each of the first split pillars has a first upstream side and a first downstream side, and includes two first parts that are spaced apart from each other to define a first micro-gap.
    Type: Application
    Filed: April 11, 2024
    Publication date: October 24, 2024
    Inventors: Chen-Yi LEE, I-Fang CHENG, Pei-Mei LU, Chao-Hong CHEN, Jyun-Hong WANG, Meng-Yen TSAI
  • Publication number: 20240236527
    Abstract: An image sensor chip with depth information is provided. The image sensor chip includes an SPAD array, a time-to-digital converter module, a storage circuit, and a data processing circuit. The SPAD array includes a plurality of image sensor units, and each of the image sensor units includes a plurality of SPAD units and a decision circuit, wherein each of the SPAD units outputs a photon detection result within a scan period, and the decision circuit generates an image-sensing signal based on the photon detection results. The time-to-digital converter module generates a plurality of first time data in response to the image-sensing signals. The storage circuit stores the first time data temporarily. The data processing unit reads the first time data from the storage circuit and generates a plurality of second time data in response to the first time data.
    Type: Application
    Filed: March 28, 2023
    Publication date: July 11, 2024
    Inventors: Chen-Yi LEE, Hsi-Hao HUANG, Tzu-Yun HUANG
  • Publication number: 20240234410
    Abstract: A semiconductor ESD protection device includes a pair of source regions, a pair of gate structures, a drain region, a plurality of first conductive contacts, a plurality of second conductive contacts, a plurality of third conductive contacts, and a dummy structure. The pair of gate structures are disposed between the pair of source regions and extend along a direction. The drain region is disposed between the pair of gate structures. Each of the first conductive contacts is disposed on one of the pair of source regions and is arranged along the direction. Each of the plurality of second conductive contacts is disposed on one of the pair of gate structures. The plurality of third conductive contacts are disposed on the drain region and arranged along the direction. The dummy structure is disposed over the drain region and between the gate structures and between the third conductive contacts.
    Type: Application
    Filed: January 9, 2023
    Publication date: July 11, 2024
    Inventors: SHENG-FU HSU, CHEN-YI LEE, LIN-YU HUANG, SHIH-FAN CHEN