Patents by Inventor Chen-Yi Lee

Chen-Yi Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240137671
    Abstract: An image sensor chip with depth information is provided. The image sensor chip includes an SPAD array, a time-to-digital converter module, a storage circuit, and a data processing circuit. The SPAD array includes a plurality of image sensor units, and each of the image sensor units includes a plurality of SPAD units and a decision circuit, wherein each of the SPAD units outputs a photon detection result within a scan period, and the decision circuit generates an image-sensing signal based on the photon detection results. The time-to-digital converter module generates a plurality of first time data in response to the image-sensing signals. The storage circuit stores the first time data temporarily. The data processing unit reads the first time data from the storage circuit and generates a plurality of second time data in response to the first time data.
    Type: Application
    Filed: March 27, 2023
    Publication date: April 25, 2024
    Inventors: Chen-Yi LEE, Hsi-Hao HUANG, Tzu-Yun HUANG
  • Patent number: 11957064
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.
    Type: Grant
    Filed: October 18, 2022
    Date of Patent: April 9, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
  • Publication number: 20240096812
    Abstract: A method of forming a semiconductor device includes arranging a semi-finished substrate, which has been tested and is known to be good, on a carrier substrate. Encapsulating the semi-finished substrate in a first encapsulant and arranging at least one semiconductor die over the semi-finished substrate. Electrically coupling at least one semiconductor component of the at least one semiconductor die to the semi-finished substrate and encasing the at least one semiconductor die and portions of the first encapsulant in a second encapsulant. Removing the carrier substrate from the semi-finished substrate and bonding a plurality of external contacts to the semi-finished substrate.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Jiun Yi Wu, Chen-Hua Yu, Chung-Shi Liu, Chien-Hsun Lee
  • Publication number: 20240081157
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.
    Type: Application
    Filed: November 6, 2023
    Publication date: March 7, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
  • Publication number: 20240074328
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Applicant: United Microelectronics Corp.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
  • Publication number: 20230360175
    Abstract: A portable video display apparatus that adopts a L-layer processing architecture and performs the following operations for each layer of x1th layer to x2th layer: generating an optical flow map between a first and a second image frames, generating a primary rectified feature map according to a first feature map of the first image frame and the optical flow map, generating an advanced rectified feature map according to the optical flow map, the primary rectified feature map, and a second feature map of the second image frame, and generating a second feature map for the next layer according to the second feature map and the advanced rectified feature map. The portable video display apparatus generates an enlarged image frame by up-sampling the second image frame, generates a display image frame according to the second feature map at the x2+1th layer and the enlarged image frame and displays it.
    Type: Application
    Filed: August 16, 2022
    Publication date: November 9, 2023
    Inventors: Chen-Yi LEE, Eugene Eu Tzuan LEE
  • Publication number: 20230356219
    Abstract: Microfluidic chips, microfluidic processing systems, and microfluidic processing methods are provided. A microfluidic chip includes a top plate and a microelectrode dot array arranged under the top plate. The microelectrode dot array includes microelectrode devices connected in a series. Each microelectrode device includes a microfluidic electrode under the top plate, a multi-functional electrode under the microfluidic electrode, and a control circuit under the multi-functional electrode. Each control circuit includes a first storage circuit, a second storage circuit, a microfluidic control and location-sensing circuit, and a temperature and magnetic control circuit. Each first storage circuit reads in a sample operation configuration. Each second storage circuit reads in a magnetic field control configuration. Each microfluidic control and location-sensing circuit enters a sample control status corresponding to a sample operation configuration.
    Type: Application
    Filed: March 15, 2023
    Publication date: November 9, 2023
    Inventors: Chen-Yi LEE, Yun-Sheng CHAN
  • Patent number: 11699618
    Abstract: The present disclosure describes a method for forming a nitrogen-rich protective layer within a low-k layer of a metallization layer to prevent damage to the low-k layer from subsequent processing operations. The method includes forming, on a substrate, a metallization layer having conductive structures in a low-k dielectric. The method further includes forming a capping layer on the conductive structures, where forming the capping layer includes exposing the metallization layer to a first plasma process to form a nitrogen-rich protective layer below a top surface of the low-k dielectric, releasing a precursor on the metallization layer to cover top surfaces of the conductive structures with precursor molecules, and treating the precursor molecules with a second plasma process to dissociate the precursor molecules and form the capping layer. Additionally, the method includes forming an etch stop layer to cover the capping layer and top surfaces of the low-k dielectric.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: July 11, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Yi Lee, Chia-Lin Hsu
  • Patent number: 11688804
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has a source region and a drain region in a substrate, a gate structure and a metallic line. The source region surrounds the drain region in the substrate. The gate structure is disposed on the substrate, and disposed between the source region and the drain region. The gate structure surrounds the drain region. The metallic line is located above the source and drain regions and the gate structure and electrically connected to the drain region or the source region. The source region includes a doped region having a break region located between two opposite ends of the doped region. The metallic line extends from the drain region, across the gate structure and across the break region and beyond the source region.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: June 27, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Cheng Chiu, Tien-Sheng Lin, Sheng-Fu Hsu, Chen-Yi Lee, Chiu-Hua Chung
  • Publication number: 20230174255
    Abstract: An unmanned aerial vehicle and a landing method for unmanned aerial vehicle are provided. The unmanned aerial vehicle includes a positioning device and a processor. When the processor detects a fight status of the unmanned aerial vehicle, the processor obtains a current coordinate from the positioning device. According to the current coordinate, a predetermined route, and a plurality of emergency landing coordinates, the processor calculates a plurality of distances for the unmanned aerial vehicle moving from the current coordinate to each of the emergency landing coordinates along the predetermined route. According to a shortest distance among the plurality of distances, the processor obtains a target emergency landing coordinate. The processor controls the unmanned aerial vehicle to move to the target emergency landing coordinate along the predetermined route.
    Type: Application
    Filed: November 28, 2022
    Publication date: June 8, 2023
    Applicant: Coretronic Intelligent Robotics Corporation
    Inventors: Ssu-Ming Chen, Ta-Ho Huang, Chen-Yi Lee
  • Patent number: 11632231
    Abstract: A substitute box includes a target input terminal, an obfuscation input terminal, a first output terminal and a second output terminal. The target input terminal is configured to receive a target input data. The obfuscation input terminal is configured to receive an obfuscation input data unrelated to a plaintext. The first output terminal is configured to output a first output data. The second output terminal is configured to output a second output data associated with the first output data. The first output data and the second output data are generated according to both the target input data and the obfuscation input data.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: April 18, 2023
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Wei Chiang, Hsi-Chia Chang, Chen-Yi Lee
  • Publication number: 20220367259
    Abstract: The present disclosure describes a method for forming a nitrogen-rich protective layer within a low-k layer of a metallization layer to prevent damage to the low-k layer from subsequent processing operations. The method includes forming, on a substrate, a metallization layer having conductive structures in a low-k dielectric. The method further includes forming a capping layer on the conductive structures, where forming the capping layer includes exposing the metallization layer to a first plasma process to form a nitrogen-rich protective layer below a top surface of the low-k dielectric, releasing a precursor on the metallization layer to cover top surfaces of the conductive structures with precursor molecules, and treating the precursor molecules with a second plasma process to dissociate the precursor molecules and form the capping layer. Additionally, the method includes forming an etch stop layer to cover the capping layer and top surfaces of the low-k dielectric.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Yi LEE, Chia-Lin HSU
  • Patent number: 11467081
    Abstract: A device and method for detecting particles by using electrical impedance measurement, in particular, relating to an improved electrical impedance measurement microfluidic chip and an improved particle detection method. The device comprises a sample injection part, a main channel (4) and an electrical impedance detection part. By means of said device and method, the present invention can accurately distinguish, detect and count different particles.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: October 11, 2022
    Assignee: NANJING YITIAN BIOTECHNOLOGY CO., LTD.
    Inventors: Chen-Yi Lee, Chao-Hong Chen, Chun-Kai Chiang, Yi Lu
  • Publication number: 20220297131
    Abstract: A microelectrode device, microfluidic chip, and microfluidic examination method are provided. The microfluidic chip includes a top plate and a microelectrode dot array having several microelectrode devices. Each microelectrode device includes a microfluidic electrode, heating electrode, and control circuit. The control circuit includes a microfluidic control and location sensing circuit, storage circuit, and temperature control circuit. The microfluidic control and location sensing circuit moves a sample within an enabling period of a microfluidic control signal and detects a capacitance value between the microfluidic electrode and the top plate within an enabling period of a location control signal. The storage circuit outputs the capacitance value, reads in the sample operation setup, and reads in the heating control setup within different enabling periods of the clock.
    Type: Application
    Filed: December 2, 2021
    Publication date: September 22, 2022
    Inventor: Chen-Yi LEE
  • Publication number: 20220297120
    Abstract: A microfluidic test system and method are provided. The microfluidic test system includes a control apparatus and a microfluidic chip. The control apparatus stores a test protocol of a biomedical test. The microfluidic chip includes a top plate and a microelectrode dot array having a plurality of microelectrode devices connected in series. The control apparatus provides a location-sensing signal to the microfluidic chip so that each microelectrode device detects a capacitance value between the top plate and the corresponding microfluidic electrode accordingly. The control apparatus provides a clock signal to the microfluidic chip so that each microelectrode device outputs the corresponding capacitance value accordingly. The control apparatus determines the size and location of a test sample within the microfluidic chip, generates a control signal according to the test protocol, the size, and the location, and provides the control signal to the microfluidic chip.
    Type: Application
    Filed: March 15, 2022
    Publication date: September 22, 2022
    Inventor: Chen-Yi LEE
  • Publication number: 20220069123
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has a source region and a drain region in a substrate, a gate structure and a metallic line. The source region surrounds the drain region in the substrate. The gate structure is disposed on the substrate, and disposed between the source region and the drain region. The gate structure surrounds the drain region. The metallic line is located above the source and drain regions and the gate structure and electrically connected to the drain region or the source region. The source region includes a doped region having a break region located between two opposite ends of the doped region. The metallic line extends from the drain region, across the gate structure and across the break region and beyond the source region.
    Type: Application
    Filed: March 4, 2021
    Publication date: March 3, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Cheng Chiu, Tien-Sheng Lin, Sheng-Fu Hsu, Chen-Yi Lee, Chiu-Hua Chung
  • Publication number: 20210281390
    Abstract: A substitute box includes a target input terminal, an obfuscation input terminal, a first output terminal and a second output terminal. The target input terminal is configured to receive a target input data. The obfuscation input terminal is configured to receive an obfuscation input data unrelated to a plaintext. The first output terminal is configured to output a first output data. The second output terminal is configured to output a second output data associated with the first output data. The first output data and the second output data are generated according to both the target input data and the obfuscation input data.
    Type: Application
    Filed: March 5, 2020
    Publication date: September 9, 2021
    Inventors: Wei Chiang, Hsi-Chia Chang, Chen-Yi Lee
  • Publication number: 20210233809
    Abstract: The present disclosure describes a method for forming a capping layer within a low-k layer of a metallization layer to prevent damage to the low-k layer from subsequent processing operations. The method includes forming, on a substrate, a metallization layer having conductive structures in a low-k dielectric. The method further includes forming a capping layer on the conductive structures, where forming the capping layer includes exposing the metallization layer to a first plasma process to form a nitrogen-rich protective layer below a top surface of the low-k dielectric, releasing a precursor on the metallization layer to cover top surfaces of the conductive structures with precursor molecules, and treating the precursor molecules with a second plasma process to dissociate the precursor molecules and form the capping layer. Additionally, the method includes forming an etch stop layer to cover the capping layer and top surfaces of the low-k dielectric.
    Type: Application
    Filed: August 12, 2020
    Publication date: July 29, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Yi LEE, Chia-Lin HSU
  • Patent number: 10753956
    Abstract: A motion detecting device includes an accelerometer configured to generate gravitational acceleration readings associated respectively with consecutive time segments, an angular acceleration sensor and configured to generate angular acceleration readings, and a processor operable in one of a standby mode and an active mode. When operated in the standby mode, the processor activates the accelerometer, deactivates the angular acceleration sensor, and determines whether the user is in a substantial moving state. When determined that the user is in the substantial moving state, the processor switches to the active mode to activate both the accelerometer and said angular acceleration sensor, in order to determine the motion of the user.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: August 25, 2020
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Kelvin Yi-Tse Lai, Yu-Lin Tsai, Chen-Yi Lee
  • Publication number: 20200229719
    Abstract: A physiological sensing method and a device using the same is disclosed. The two sides of the device are respectively provided with an installed component. The device is arranged on the wrist of a user through the installed components. At least two physiological sensors, arranged in row on the installed component, generate and transmit original physiological signals to a controller. The controller filters out the original physiological signals to generate two basic energy values, multiplies the two basic physiological parameters by the two basic energy values to generate two basic estimation parameters, and substitutes the two basic energy values into a standard physiological value equation to generate a standard physiological value.
    Type: Application
    Filed: June 14, 2019
    Publication date: July 23, 2020
    Inventors: CHEN-YI LEE, EUGENE LEE, TSU JUI HSU