Abstract: A method of performing an ultraviolet (UV) curing process on an interfacial layer over a semiconductor substrate, the method includes supplying a gas flow rate ranging from 10 standard cubic centimeters per minute (sccm) to 5 standard liters per minute (slm), wherein the gas comprises inert gas. The method further includes heating the interfacial layer at a temperature less than or equal to 700° C. Another method of performing an annealing process on an interfacial layer over a semiconductor substrate, the second method includes supplying a gas flow rate ranging from 10 sccm to 5 slm, wherein the gas comprises inert gas. The method further includes heating the interfacial layer at a temperature less than or equal to 600° C.

Abstract: A digital sensing apparatus includes a sensing unit capable of providing a sensing response associated with an environmental parameter, and a digital readout module including a reading unit for generating a pulse signal having a pulse width as sociated with the sensing response, and a converting unit. The converting unit includes a clock signal generator for generating a variable-frequency clock signal, and a counter operable to count a width value of the pulse width of the pulse signal using the clock signal, so as to generate a digital sensing code. The frequency of the clock signal from the clock signal generator is adjustable to adjust resolution of the width value of the pulse width of the pulse signal.

Abstract: This description relates to a method including forming an interfacial layer over a semiconductor substrate. The method further includes etching back the interfacial layer. The method further includes performing an ultraviolet (UV) curing process on the interfacial layer. The UV curing process includes supplying a gas flow rate ranging from 10 standard cubic centimeters per minute (sccm) to 5 standard liters per minute (slm), wherein the gas comprises inert gas, and heating the interfacial layer at a temperature less than or equal to 700° C. The method further includes depositing a high-k dielectric material over the interfacial layer.

Abstract: A delay cell includes a first inverted transistor pair, a second inverted transistor pair and a plurality of delay units. The first inverted transistor pair is used to receive an input signal. The second inverted transistor pair is electrically cross-coupled to the first inverted transistor pair and cross-controlled by the first inverted transistor pair. The delay units are cascaded between the first inverted transistor pair and between the second inverted transistor pair, thereby providing a plurality of signal propagation delays sequentially, wherein the input signal is delayed for a pre-determined time by the first inverted transistor pair, the second inverted transistor pair and the delay units which are operated sequentially, thereby creating an output signal corresponding to the pre-determined time. A digitally controlled oscillator including the aforementioned delay cells is provided.

Abstract: In a cyclic code decoding method, a decoder analyzes a received codeword to identify unreliable symbols in the codeword, and sets candidate syndrome patterns accordingly. Then, a syndrome calculator calculates evaluated syndrome values associated with one of the candidate syndrome patterns, and an error location polynomial (ELP) generator generates an ELP according to the syndrome values. An error correction device corrects the errors in the codeword according to the ELP when a degree of the ELP is not more than a threshold value, and the syndrome calculator adjusts the syndrome values and the ELP generator generates another ELP according to the adjusted syndrome values when otherwise.

Abstract: A delay cell includes a first inverted transistor pair, a second inverted transistor pair and a plurality of delay units. The first inverted transistor pair is used to receive an input signal. The second inverted transistor pair is electrically cross-coupled to the first inverted transistor pair and cross-controlled by the first inverted transistor pair. The delay units are cascaded between the first inverted transistor pair and between the second inverted transistor pair, thereby providing a plurality of signal propagation delays sequentially, wherein the input signal is delayed for a pre-determined time by the first inverted transistor pair, the second inverted transistor pair and the delay units which are operated sequentially, thereby creating an output signal corresponding to the pre-determined time. A digitally controlled oscillator including the aforementioned delay cells is provided.

Abstract: For a large size FFT computation, this invention decomposes it into several smaller sizes FFT by decomposition equation and then transform the original index from one dimension into multi-dimension vector. By controlling the index vector, this invention could distribute the input data into different memory banks such that both the in-place policy for computation and the multi-bank memory for high-radix structure could be supported simultaneously without memory conflict. Besides, in order to keep memory conflict-free when the in-place policy is also adopted for I/O data, this invention reverses the decompose order of FFT to satisfy the vector reverse behavior. This invention can minimize the area and reduce the necessary clock rate effectively for general sized memory-based FFT processor design.

Abstract: This description relates to a method including forming an interfacial layer over a semiconductor substrate. The method further includes etching back the interfacial layer. The method further includes performing an ultraviolet (UV) curing process on the interfacial layer. The UV curing process includes supplying a gas flow rate ranging from 10 standard cubic centimeters per minute (sccm) to 5 standard liters per minute (slm), wherein the gas comprises inert gas, and heating the interfacial layer at a temperature less than or equal to 700° C. The method further includes depositing a high-k dielectric material over the interfacial layer.

Abstract: A semiconductor structure includes a semiconductor substrate having a first portion and a second portion. A first Fin field-effect transistor (FinFET) is formed over the first portion of the semiconductor substrate, wherein the first FinFET includes a first fin having a first fin height. A second FinFET is formed over the second portion of the semiconductor substrate, wherein the second FinFET includes a second fin having a second fin height different from the first fin height. A top surface of the first fin is substantially level with a top surface of the second fin. A punch-through stopper is underlying and adjoining the first FinFET, wherein the punch-through stopper isolates the first fin from the first portion of the semiconductor substrate.

Abstract: A method for reducing interfacial layer (IL) thickness for high-k dielectrics and metal gate stack is provided. In one embodiment, the method includes forming an interfacial layer on a semiconductor substrate, etching back the interfacial layer, depositing a high-k dielectric material over the interfacial layer, and forming a metal gate over the high-k dielectric material. The IL can be chemical oxide, ozonated oxide, thermal oxide, or formed by ultraviolet ozone (UVO) oxidation process from chemical oxide, etc. The etching back of IL can be performed by a Diluted HF (DHF) process, a vapor HF process, or any other suitable process. The method can further include performing UV curing or low thermal budget annealing on the interfacial layer before depositing the high-k dielectric material.

Abstract: A semiconductor structure includes a semiconductor substrate having a first portion and a second portion. A first Fin field-effect transistor (FinFET) is formed over the first portion of the semiconductor substrate, wherein the first FinFET includes a first fin having a first fin height. A second FinFET is formed over the second portion of the semiconductor substrate, wherein the second FinFET includes a second fin having a second fin height different from the first fin height. A top surface of the first fin is substantially level with a top surface of the second fin. A punch-through stopper is underlying and adjoining the first FinFET, wherein the punch-through stopper isolates the first fin from the first portion of the semiconductor substrate.

Abstract: An electronic device and a method for protecting against a differential power analysis attack are disclosed herein. The electronic device includes an encryption/decryption unit, a random number generator and a countermeasure circuit. The encryption/decryption unit can provide an enable signal when encrypting or decrypting more bits of data. The random number generator can generate random data. When receiving the enable signal, the countermeasure circuit can operate according to the bits of data and the random data.

Abstract: A method of forming a semiconductor structure includes providing a composite substrate, which includes a bulk silicon substrate and a silicon germanium (SiGe) layer over and adjoining the bulk silicon substrate. A first condensation is performed to the SiGe layer to form a condensed SiGe layer, so that the condensed SiGe layer has a substantially uniform germanium concentration. The condensed SiGe layer and a top portion of the bulk silicon substrate are etched to form a composite fin including a silicon fin and a condensed SiGe fin over the silicon fin. The method further includes oxidizing a portion of the silicon fin; and performing a second condensation to the condensed SiGe fin.

Abstract: An operating method and a circuit for low density parity check (LDPC) decoders, in which original bit nodes are incorporated into check nodes for simultaneous operation. The bit node messages are generated according to the difference between the newly generated check messages and the previous check node messages. The bit node messages can be updated immediately, and the decoder throughput can be improved. The required memory of LDPC decoders can be effectively reduced, and the decoding speed can also be enhanced.

Abstract: The invention discloses an automatic patent transaction system. The invention comprises a patent database, a member database, a match computing device, a share computing device, a non-member database, and a licensing and transacting computing device. The operation method of the invention also comprises a method for the participation of member and non-member, and a method for the participation of member only. Thus, the invention is able to increase the trade efficiency of the patent and reduce the trade cost of the patent.

Abstract: An apparatus and a method of processing cyclic codes are disclosed herein, where the apparatus includes at least one reconfigurable module and an encoder controller. The reconfigurable module includes a plurality of linear feedback shift registers. The encoder controller can control the reconfigurable module to factor a generator polynomial into a factorial polynomial. In the reconfigurable module, the linear feedback shift registers can register a plurality of factors of the factorial polynomial respectively.

Abstract: A dual positive-feedbacks voltage controlled oscillator includes an oscillation circuit and a cross coupled pair circuit. The oscillation circuit includes a first transistor, a second transistor, an inductor and a plurality of capacitors. The gates of the first and second transistors are opposite to each other and coupled to two points of the inductor. The inductor and the capacitors are formed as a LC tank. The cross coupled pair circuit includes a third transistor and a fourth transistor. The gates of the third and fourth transistors are cross coupled to two points of the inductor. Thereby, the gate of the third transistor is coupled to the gate of the second transistor; the gate of the fourth transistor is coupled to the gate of the first transistor; the drain of the third transistor is coupled to the source of the first transistor; and the drain of the fourth transistor is coupled to the source of the second transistor.

Abstract: A method of forming a semiconductor structure includes providing a composite substrate, which includes a bulk silicon substrate and a silicon germanium (SiGe) layer over and adjoining the bulk silicon substrate. A first condensation is performed to the SiGe layer to form a condensed SiGe layer, so that the condensed SiGe layer has a substantially uniform germanium concentration. The condensed SiGe layer and a top portion of the bulk silicon substrate are etched to form a composite fin including a silicon fin and a condensed SiGe fin over the silicon fine. The method further includes oxidizing a portion of the silicon fin; and performing a second condensation to the condensed SiGe fin.

Abstract: A communication device uses a local clock generator to regenerate the carrier frequency of the reference signal from a remote communication. In particular, a closed loop is used to self-calibrate the local pulse till the frequency is fixed to be within a fixed frequency margin. Once the local pulse is obtained, the demodulator will use the local pulse to demodulate the reference signal to generate the data signal.

Abstract: A method for reducing interfacial layer (IL) thickness for high-k dielectrics and metal gate stack is provided. In one embodiment, the method includes forming an interfacial layer on a semiconductor substrate, etching back the interfacial layer, depositing a high-k dielectric material over the interfacial layer, and forming a metal gate over the high-k dielectric material. The IL can be chemical oxide, ozonated oxide, thermal oxide, or formed by ultraviolet ozone (UVO) oxidation process from chemical oxide, etc. The etching back of IL can be performed by a Diluted HF (DHF) process, a vapor HF process, or any other suitable process. The method can further include performing UV curing or low thermal budget annealing on the interfacial layer before depositing the high-k dielectric material.