Patents by Inventor Chen-Yu Cheng
Chen-Yu Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240074127Abstract: In a method of manufacturing an electronic package, first grooves are formed on a circuit structure and a second groove is formed in each of the first grooves to allow the circuit structure to become circuit layers. Owing to the second groove is narrower than the first groove, each of the circuit layers has an encircled surface and a notch located on the encircled surface. When a shielding layer is provided to cover an encapsulating body located on the circuit layer, a space of the notch is not covered by the shielding layer such that a portion to be removed of the shielding layer will not remain on the electronic package to become burr after removing the portion to be removed.Type: ApplicationFiled: July 13, 2023Publication date: February 29, 2024Inventors: Chen-Yu Wang, Pai-Sheng Cheng, Huan-Kuen Chen
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Publication number: 20230413548Abstract: A semiconductor device includes a circuit board, a bottom plate, landing pads, a stack, support pillars, and memory pillars. The circuit board includes circuit structures and wires and has a peripheral area, an array area and a staircase area disposed between the peripheral area and the array area. The bottom plate is disposed on the circuit board, and the bottom plate includes a bottom conductive layer. The landing pads are embedded in at least a top portion of the bottom conductive layer and contact the bottom conductive layer in the staircase area. The stack is disposed on the bottom plate, and includes conductive layers and insulating layers alternately stacked along a first direction. The support pillars pass through the stack along the first direction and extend to the landing pads in the staircase area. The memory pillars pass through the stack along the first direction in the array area.Type: ApplicationFiled: May 19, 2022Publication date: December 21, 2023Inventors: Chen-Yu CHENG, Tzung-Ting HAN
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Publication number: 20230292960Abstract: A kitchen container includes a container body, a cover body, a rotating mechanism, and a drive element. The rotating mechanism includes a moving rack transversely movable on the cover body, a main gear driven by the moving rack and a drive gear driven by the main gear. The drive element is connected with the drive gear. The main gear is linked with the drive gear through at least one transmission set. The transmission set is disposed on a sliding trough and is shifted with rotation of the main gear. The transmission set shifts on the sliding trough to be a linked state with the drive gear when the main gear rotates in a rotating direction, and the transmission set shifts on the sliding trough to be disengaged from the linked state with the drive gear when the main gear rotates in another rotating direction.Type: ApplicationFiled: March 18, 2022Publication date: September 21, 2023Inventors: Yi-Liang HOU, Che-Hsin LIAO, Chen-Yu CHENG
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Publication number: 20230290396Abstract: Provided is a memory device including a stack structure. The stack structure is in the memory array region of a substrate. The stack structure comprises a plurality of first insulating layers and a plurality of conductive layers stacked alternately on each other. A first staircase structure and a second staircase structure are located in a first staircase region and a second staircase region of the substrate respectively. The second staircase structure has steps descending from an upper layer proximal to the memory array region to a lower layer distal to the memory array region. Block slits and zone slit are disposed over the substrate in the second staircase region. The block slits divide the stack structure, the first staircase structure and the second staircase structure into memory blocks. The zone slits divide one of the memory blocks into a plurality of zones separately within the memory blocks.Type: ApplicationFiled: May 18, 2023Publication date: September 14, 2023Applicant: Macronix International Co., Ltd.Inventors: Chen-Yu Cheng, Tzung-Ting Han
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Patent number: 11727971Abstract: A memory device includes a substrate, a stack structure, a first staircase structure, and a first part of a second staircase structure. The substrate includes a plurality of blocks each having a staircase region, a memory array region, and a word line cutting region. The stack structure is located on the substrate in the memory array region, and includes first insulating layers and conductive layers alternately stacked on each other. The first staircase structure is located on the substrate in the staircase region, and includes first insulating layers and conductive layers alternately stacked on each other. The first part of the second staircase structure is located on the substrate in the word line cutting region, and includes first insulating layers and conductive layers alternately stacked on each other, and two first parts of two second staircase structures in two adjacent blocks are separated from each other.Type: GrantFiled: December 22, 2020Date of Patent: August 15, 2023Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chen-Yu Cheng, Tzung-Ting Han
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Publication number: 20230187359Abstract: Provided is a memory device including a substrate, a stack structure, a plurality of pads and an additional dielectric layer. The substrate has an array region and a staircase region. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The pads are disposed on the substrate in the staircase region. The pads are respectively connected to the conductive layers, so as to form a staircase structure. The additional dielectric layer is disposed on the stack structure to contact a topmost conductive layer of the conductive layers. A topmost pad of the pads includes a landing portion to contact a plug and an extension portion. The landing portion is laterally adjacent to the additional dielectric layer, and the extension portion extends over a top surface of the additional dielectric layer.Type: ApplicationFiled: February 6, 2023Publication date: June 15, 2023Applicant: MACRONIX International Co., Ltd.Inventors: Ching Hung Wang, Shih Chin Lee, Chen-Yu Cheng, Tzung-Ting Han
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Patent number: 11610842Abstract: Provided is a memory device including a substrate, a stack structure, a plurality of pads, and a protective layer. The substrate has an array region and a staircase region. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The pads are disposed on the substrate in the staircase region. The pads are respectively connected to the conductive layers, so as to form a staircase structure. The protective layer is disposed on the stack structure to contact a topmost conductive layer. A top surface of the protective layer adjacent to a topmost pad has a curved profile.Type: GrantFiled: December 2, 2020Date of Patent: March 21, 2023Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Ching Hung Wang, Shih Chin Lee, Chen-Yu Cheng, Tzung-Ting Han
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Publication number: 20230055997Abstract: A processor assembly including: an exposure station operable to expose a sample on a slide; a print station operable to apply a reagent to the exposed sample through a thermal inkjet process; and a robotic transfer mechanism to transfer the slide from the exposure station to the print station. Also, a reagent cartridge including: a body defining a container having a volume therein; a nonmetallic bag in the container operable to contain a reagent; and a printhead at a base of the body, the printhead coupled to an outlet of the bag. Further, a method including exposing a sample on a slide in a processor assembly; robotically transferring the slide to a printing station of the processor assembly; and applying a reagent to the exposed sample at the printing station by a thermal inkjet printing process.Type: ApplicationFiled: December 31, 2020Publication date: February 23, 2023Applicant: Sakura Finetek U.S.A., Inc.Inventors: Amit D. SHAH, Scott WEBSTER, Cristina R. FLORES, Chen Yu CHENG, Chia Hsien LIN, Chih Shun CHUANG, Nicholas John BOOKER, Andrew Douglas WATKINS, Rebecca Jean BARTEL, Chester John HENDERSON, Erico VON BUEREN, Michael YANG
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Patent number: 11515319Abstract: Methods and apparatus for fabricating memory devices are provided. In one aspect, an intermediate stack of dielectric layers are formed on a first stack of dielectric layers in a first tier. The intermediate stack of dielectric layers is then partially or fully etched and have a landing pad layer deposited thereon. In response to planarizing the landing pad layer to expose a top surface of the intermediate stack of dielectric layers, a second stack of dielectric layers are deposited above the planarized landing pad layer. A staircase is formed by etching through the second stack, the intermediate stack, and the first stack of dielectric layers in the staircase region of the memory device. The staircase is located adjacent to one end of the center landing pad, where steps of the staircase are formed within the thickness of the center landing pad.Type: GrantFiled: May 5, 2020Date of Patent: November 29, 2022Assignee: Macronix International Co., Ltd.Inventors: Chen-Yu Cheng, Tzung-Ting Han
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Publication number: 20220199134Abstract: A memory device includes a substrate, a stack structure, a first staircase structure, and a first part of a second staircase structure. The substrate includes a plurality of blocks each having a staircase region, a memory array region, and a word line cutting region. The stack structure is located on the substrate in the memory array region, and includes first insulating layers and conductive layers alternately stacked on each other. The first staircase structure is located on the substrate in the staircase region, and includes first insulating layers and conductive layers alternately stacked on each other. The first part of the second staircase structure is located on the substrate in the word line cutting region, and includes first insulating layers and conductive layers alternately stacked on each other, and two first parts of two second staircase structures in two adjacent blocks are separated from each other.Type: ApplicationFiled: December 22, 2020Publication date: June 23, 2022Applicant: MACRONIX International Co., Ltd.Inventors: Chen-Yu Cheng, Tzung-Ting Han
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Publication number: 20220173040Abstract: Provided is a memory device including a substrate, a stack structure, a plurality of pads, and a protective layer. The substrate has an array region and a staircase region. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The pads are disposed on the substrate in the staircase region. The pads are respectively connected to the conductive layers, so as to form a staircase structure. The protective layer is disposed on the stack structure to contact a topmost conductive layer. A top surface of the protective layer adjacent to a topmost pad has a curved profile.Type: ApplicationFiled: December 2, 2020Publication date: June 2, 2022Applicant: MACRONIX International Co., Ltd.Inventors: Ching Hung Wang, Shih Chin Lee, Chen-Yu Cheng, Tzung-Ting Han
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Publication number: 20210351196Abstract: Methods and apparatus for fabricating memory devices are provided. In one aspect, an intermediate stack of dielectric layers are formed on a first stack of dielectric layers in a first tier. The intermediate stack of dielectric layers is then partially or fully etched and have a landing pad layer deposited thereon. In response to planarizing the landing pad layer to expose a top surface of the intermediate stack of dielectric layers, a second stack of dielectric layers are deposited above the planarized landing pad layer. A staircase is formed by etching through the second stack, the intermediate stack, and the first stack of dielectric layers in the staircase region of the memory device. The staircase is located adjacent to one end of the center landing pad, where steps of the staircase are formed within the thickness of the center landing pad.Type: ApplicationFiled: May 5, 2020Publication date: November 11, 2021Applicant: Macronix International Co., Ltd.Inventors: Chen-Yu Cheng, Tzung-Ting Han
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Publication number: 20190239484Abstract: A dairy cowshed monitoring system includes a cooling system having a plurality of operating modes, at least one image sensor, at least one temperature/humidity sensor, and a control circuit. The image sensor is for collecting image data in a dairy cowshed and obtaining a cow drinking water frequency in the dairy cowshed. The temperature/humidity sensor is for collecting a temperature and a humidity in the dairy cowshed and calculating a temperature/humidity index according to the temperature and the humidity. The control circuit is coupled to the cooling system, the image sensor and the temperature/humidity sensor and for receiving the image data, the cow drinking water frequency and the temperature/humidity index and determining whether to activate and control the cooling system in one of the operating modes to cool the dairy cowshed according to the cow drinking water frequency and the temperature/humidity index.Type: ApplicationFiled: April 24, 2018Publication date: August 8, 2019Inventors: Yu-Chi Tsai, Chen-Yu Cheng, Jih-Tay Hsu, Shih-Torng Ding, Ta-Te Lin
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Patent number: 9748332Abstract: A semiconductor device includes a semiconductor substrate, multiple memory cells on the semiconductor substrate arranged along a first dimension and along a second dimension that is orthogonal to the first dimension, in which each memory cell of the multiple memory cells includes a channel region in the semiconductor substrate, a tunnel dielectric layer on the channel region, and a first electrode layer on the tunnel dielectric layer. Along the first dimension, the channel region of each memory cell of the multiple memory cells is separated from the channel region of an adjacent memory cell of the multiple memory cells by a corresponding first air gap, each first air gap extending from below an upper surface of the semiconductor substrate up to an inter-electrode dielectric layer.Type: GrantFiled: December 9, 2016Date of Patent: August 29, 2017Assignee: Macronix International Co., Ltd.Inventors: Chih Kai Yang, Chen Yu Cheng, Shih Chin Lee, Ching Hung Wang, Tzung-Ting Han
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Patent number: 6607265Abstract: An ink print head has an ink container for storing fluid, a chip installed at a bottom of the ink container having a central slot for passing fluid, and a dry film formed on the chip having a plurality of ink chambers. The ink print head also has a nozzle plate formed below the dry film, a middle portion of the nozzle plate protruding above the nozzle plate so as to form a central refill chamber, a plurality of nozzles corresponding to the ink chambers of the dry film, and a plurality of heaters set on the chip for heating fluid inside the ink chambers so that the fluid can be ejected from the nozzles of the nozzle plate. The fluid inside the ink container will flow through the central slot into the central refill chamber and then into the ink chambers.Type: GrantFiled: January 3, 2002Date of Patent: August 19, 2003Assignee: International United Technology Co., Ltd.Inventors: Chieh-Wen Wang, I-Chung Hou, Yi-Hsuan Lai, Chen-Yu Cheng
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Patent number: 6469900Abstract: The locking and ejecting apparatus includes a latching mechanism, an ejection mechanism, a first string and a second string. The latching mechanism is for locking the module device in a locked position or unlocking the module device from the locked position. The ejection mechanism is for ejecting the module device on disengagement of the latching mechanism from the locked position. During the unlocking and ejecting operations, the second button is pulled right after the first button is pressed. After the module device is released from the locked position and ejected out of the internal bay, the first spring positioned to generate a first force restores the latching mechanism and the second spring positioned to generate a second force restores the ejection mechanism.Type: GrantFiled: January 17, 2001Date of Patent: October 22, 2002Assignee: Quanta Computer, Inc.Inventor: Chen Yu Cheng
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Publication number: 20020122089Abstract: An ink print head has an ink container for storing fluid, a chip installed at a bottom of the ink container having a central slot for passing fluid, and a dry film formed on the chip having a plurality of ink chambers. The ink print head also has a nozzle plate formed below the dry film, a middle portion of the nozzle plate protruding above the nozzle plate so as to form a central refill chamber, a plurality of nozzles corresponding to the ink chambers of the dry film, and a plurality of heaters set on the chip for heating fluid inside the ink chambers so that the fluid can be ejected from the nozzles of the nozzle plate. The fluid inside the ink container will flow through the central slot into the central refill chamber and then into the ink chambers.Type: ApplicationFiled: January 3, 2002Publication date: September 5, 2002Inventors: Chieh-Wen Wang, I-Chung Hou, Yi-Hsuan Lai, Chen-Yu Cheng
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Patent number: 6431687Abstract: A manufacturing method of monolithic integrated thermal bubble inkjet print heads and the structure for the same. The method utilizes semiconductor manufacturing technologies to configure various elements in a thermal bubble inkjet print head, such as ink channels, an ink slot, an energy transducer, an orifice plate, on a single substrate. The ink channels are formed on an top surface of the substrate using the anisotropic etching technique. The ink slot is formed on a back surface of the substrate using the anisotropic etching technique. The energy transducer and the orifice plate are formed in order above the ink channels using the coating and etching techniques. This thermal bubble inkjet print head manufacturing method is particularly useful in the all batch process without employing the steps of precision alignment joint for the orifice plate in a conventional inkjet print head. Therefore, the method can greatly increase production efficiency and lower production costs.Type: GrantFiled: March 20, 2001Date of Patent: August 13, 2002Assignee: Industrial Technology Research InstituteInventors: Dong-Sing Wuu, Chen-Yu Cheng, Je-Ping Hu, Yi-Yung Wu, Yih-Shing Lee
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Publication number: 20020093792Abstract: The locking and ejecting apparatus includes a latching mechanism, an ejection mechanism, a first string and a second string. The latching mechanism is for locking the module device in a locked position or unlocking the module device from the locked position. The ejection mechanism is for ejecting the module device on disengagement of the latching mechanism from the locked position. During the unlocking and ejecting operations, the second button is pulled right after the first button is pressed. After the module device is released from the locked position and ejected out of the internal bay, the first spring positioned to generate a first force restores the latching mechanism and the second spring positioned to generate a second force restores the ejection mechanism.Type: ApplicationFiled: January 17, 2001Publication date: July 18, 2002Inventor: Chen Yu Cheng
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Publication number: 20020075359Abstract: A manufacturing method of monolithic integrated thermal bubble inkjet print heads and the structure for the same. The method utilizes semiconductor manufacturing technologies to configure various elements in a thermal bubble inkjet print head, such as ink channels, an ink slot, an energy transducer, an orifice plate, on a single substrate. The ink channels are formed on an top surface of the substrate using the anisotropic etching technique. The ink slot is formed on a back surface of the substrate using the anisotropic etching technique. The energy transducer and the orifice plate are formed in order above the ink channels using the coating and etching techniques. This thermal bubble inkjet print head manufacturing method is particularly useful in the all batch process without employing the steps of precision alignment joint for the orifice plate in a conventional inkjet print head. Therefore, the method can greatly increase production efficiency and lower production costs.Type: ApplicationFiled: March 20, 2001Publication date: June 20, 2002Inventors: Dong-Sing Wuu, Chen-Yu Cheng, Je-Ping Hu, Yi-Yung Wu, Yih-Shing Lee