Patents by Inventor Chen-Yu Wang

Chen-Yu Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250125716
    Abstract: A calibration circuit of a pulse-frequency modulation (PFM) converter includes a signal generator circuit and a calibration control circuit. The signal generator circuit generates and outputs an emulated slope signal to a comparator circuit under a calibration mode, wherein the emulated slope signal has an emulated slope following an initial voltage, and the emulated slope corresponds to a slope of a sensed signal indicative of electrical characteristic of an inductor of the PFM converter. The calibration control circuit refers to an output signal that is generated from a PFM control circuit in response to an output signal of the comparator circuit, to calibrate at least one circuit of the PFM converter.
    Type: Application
    Filed: October 7, 2024
    Publication date: April 17, 2025
    Applicant: Airoha Technology Corp.
    Inventors: Chen-Yu Wang, Ke-Deng Huang
  • Patent number: 12224183
    Abstract: A package including a first carrier, a seed layer, wires, a die and a molding material is provided. The first carrier is removed to expose the seed layer after disposing a second carrier on the molding material, then the seed layer is removed to expose the wires, and a gold layer is deposited on each of the wires by immersion gold plating, finally a semiconductor device is obtained. The gold layer is provided to protect the wires from oxidation and improve solder joint reliability.
    Type: Grant
    Filed: August 26, 2022
    Date of Patent: February 11, 2025
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Shrane-Ning Jenq, Wen-Cheng Hsu, Chen-Yu Wang, Chih-Ming Kuo, Chwan-Tyaw Chen, Lung-Hua Ho
  • Patent number: 12146049
    Abstract: A styrene-isoprene/butadiene diblock copolymer contains a polystyrene block and a polyisoprene/butadiene block. Based on 100 wt % of the styrene-isoprene/butadiene diblock copolymer, the polystyrene block is 20-45 wt %, and the polyisoprene/butadiene block is 55-80 wt %. The polyisoprene/butadiene block has a polyisoprene unit and a polybutadiene unit. The weight ratio of the polyisoprene unit to the polybutadiene unit is 8:2 to 2:8.
    Type: Grant
    Filed: April 5, 2022
    Date of Patent: November 19, 2024
    Assignee: LCY CHEMICAL CORP.
    Inventors: Yi-Cheng Wan, Chen-Yu Wang
  • Publication number: 20240194646
    Abstract: A semiconductor package includes a substrate, first bumps, a first chip, metal pillars, second bumps and a second chip. The substrate includes first and second conductive pads which are located on a top surface of the substrate. Both ends of the first bumps are connected to the first conductive pads and the first chip, respectively. Both ends of the metal pillars are connected to the second conductive pads and one end of the second bumps, respectively. A cross-sectional area of each of the metal pillars is larger than that of each of the second bumps. The second chip is connected to the other end of the second bumps and located above the first chip.
    Type: Application
    Filed: September 29, 2023
    Publication date: June 13, 2024
    Inventors: Chin-Tang Hsieh, Lung-Hua Ho, Chih-Ming Kuo, Chen-Yu Wang, Chih-Hao Chiang, Pai-Sheng Cheng, Kung-An Lin, Chun-Ting Kuo, Yu-Hui Hu, Wen-Cheng Hsu
  • Publication number: 20240105664
    Abstract: A package structure includes a first RDL, an adhesive layer and a first electronic component. Upper bumps and conductive pads are provided on a first upper surface and a first lower surface of the first RDL, respectively. The adhesive layer is located on the first upper surface of the first RDL and surrounds the upper bumps. The first electronic component is mounted on the adhesive layer and includes conductors which are visible from an active surface of the first electronic component and joined to the upper bumps, the active surface of the first electronic component faces toward the first upper surface of the first RDL. Two adhesive surfaces of the adhesive layer are adhered to the first upper surface of the first RDL and the active surface of the first electronic component, respectively.
    Type: Application
    Filed: August 16, 2023
    Publication date: March 28, 2024
    Inventors: Yu-Chung Huang, Hsin-Yen Tsai, Fa-Chung Chen, Cheng-Fan Lin, Chen-Yu Wang
  • Publication number: 20240074127
    Abstract: In a method of manufacturing an electronic package, first grooves are formed on a circuit structure and a second groove is formed in each of the first grooves to allow the circuit structure to become circuit layers. Owing to the second groove is narrower than the first groove, each of the circuit layers has an encircled surface and a notch located on the encircled surface. When a shielding layer is provided to cover an encapsulating body located on the circuit layer, a space of the notch is not covered by the shielding layer such that a portion to be removed of the shielding layer will not remain on the electronic package to become burr after removing the portion to be removed.
    Type: Application
    Filed: July 13, 2023
    Publication date: February 29, 2024
    Inventors: Chen-Yu Wang, Pai-Sheng Cheng, Huan-Kuen Chen
  • Publication number: 20230420287
    Abstract: A clamp assembly includes at least one clamp which is provided to clamp a workpiece in electroless plating, etching, electroplating or cleaning process. The clamp includes a base, a clamping element and a limiting element. The base is mounted on a carrier and includes a guide hole and a first limiting hole which are communicated with each other. The clamping element includes a guide rod and a second limiting hole, the guide rod is inserted into the guide hole to allow the second limiting hole located on the guide hole to be communicated with the first limiting hole. The limiting element is inserted into the first and second limiting holes to integrate the base with the clamping element for clamping the workpiece.
    Type: Application
    Filed: April 21, 2023
    Publication date: December 28, 2023
    Inventors: Ching-Wen Chen, Chen-Lung Teng, Kung-An Lin, Chen-Yu Wang
  • Publication number: 20230378044
    Abstract: A flip-chip bonding structure includes a substrate and a chip. A lead of the substrate includes a body, a hollow opening, a bonding island and at least one connecting bridge. The hollow opening is in the body and surrounded by the body. The bonding island is located in the hollow opening such that there is a hollow space in the hollow opening and located between the body and the bonding island. The connecting bridge is located in the hollow space to connect the body and the bonding island. A bump of the chip is bonded to the bonding island by a solder. The solder is restricted on the bonding island and separated from the body by the hollow space so as to avoid the solder from overflowing to the body and avoid the chip from shifting.
    Type: Application
    Filed: February 14, 2023
    Publication date: November 23, 2023
    Inventors: Chin-Tang Hsieh, Lung-Hua Ho, Chih-Ming Kuo, Chun-Ting Kuo, Yu-Hui Hu, Chih-Hao Chiang, Chen-Yu Wang, Kung-An Lin, Pai-Sheng Cheng
  • Publication number: 20230275073
    Abstract: A package structure is provided herein, which includes a substrate, an integrated transistor, and an encapsulation structure. The integrated transistor is disposed on the substrate and includes a transistor, a capacitor, a resistor, a first Zener diode, and a second Zener diode. The transistor includes a gate, a drain, and a source. The capacitor is electrically connected to the gate, and the resistor is electrically connected to the gate. The first Zener diode includes a first anode and a first cathode electrically connected to the gate. The second Zener diode includes a second anode electrically connected to the first anode and a second cathode electrically connected to the source. The encapsulation structure encapsulates the integrated transistor. The package structure includes a gate terminal, a drain terminal, and a source terminal.
    Type: Application
    Filed: February 24, 2023
    Publication date: August 31, 2023
    Inventors: Jia-Tay KUO, Chiao FU, Sheng-Bo WANG, Chen-Yu WANG, Yao-Zhong LIU
  • Publication number: 20230187378
    Abstract: In a method of manufacturing a semiconductor package, at least one conductive wire is formed on a substrate in a wire bonding process, a ball end of the conductive wire is located above the substrate, a molding material is provided to cover the conductive wire except the ball end, and an EMI shielding layer is formed on the molding material to connect to the ball end. Owing to the ball end is exposed on the molding material, connection area of the EMI shielding layer to the conductive wire is increased to improve connection strength and reliability between the EMI shielding layer and the conductive wire.
    Type: Application
    Filed: November 17, 2022
    Publication date: June 15, 2023
    Inventors: Shrane-Ning Jenq, Chen-Yu Wang, Chin-Tang Hsieh, Shu-Yeh Chang, Lung-Hua Ho
  • Publication number: 20230135424
    Abstract: A package including a first carrier, a seed layer, wires, a die and a molding material is provided. The first carrier is removed to expose the seed layer after disposing a second carrier on the molding material, then the seed layer is removed to expose the wires, and a gold layer is deposited on each of the wires by immersion gold plating, finally a semiconductor device is obtained. The gold layer is provided to protect the wires from oxidation and improve solder joint reliability.
    Type: Application
    Filed: August 26, 2022
    Publication date: May 4, 2023
    Inventors: Shrane-Ning Jenq, Wen-Cheng Hsu, Chen-Yu Wang, Chih-Ming Kuo, Chwan-Tyaw Chen, Lung-Hua Ho
  • Publication number: 20220332937
    Abstract: A styrene-isoprene/butadiene diblock copolymer contains a polystyrene block and a polyisoprene/butadiene block. Based on 100 wt % of the styrene-isoprene/butadiene diblock copolymer, the polystyrene block is 20-45 wt %, and the polyisoprene/butadiene block is 55-80 wt %. The polyisoprene/butadiene block has a polyisoprene unit and a polybutadiene unit. The weight ratio of the polyisoprene unit to the polybutadiene unit is 8:2 to 2:8.
    Type: Application
    Filed: April 5, 2022
    Publication date: October 20, 2022
    Inventors: Yi-Cheng WAN, Chen-Yu WANG
  • Patent number: 11476772
    Abstract: A voltage converter circuit, comprising: a bridge rectifier; a first transistor, having a first end, a second end and a third end; a second transistor, having a first end and a second end; wherein the first end of the first transistor and the first end of second transistor are electrically connected to bridge rectifier, and the second end of the first transistor is electrically connected to the first end of the second transistor; and a Zener diode, connected between the third end of the first transistor and the second end of the second transistor.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: October 18, 2022
    Assignee: EPISTAR CORPORATION
    Inventors: Sheng-Bo Wang, Chiao Fu, Chang-Hsieh Wu, Jai-Tai Kuo, Chao-Kai Chang, Yao-Zhong Liu, Yi-Ru Shen, Chen-Yu Wang
  • Publication number: 20210126548
    Abstract: A voltage converter circuit, comprising: a bridge rectifier; a first transistor, having a first end, a second end and a third end; a second transistor, having a first end and a second end; wherein the first end of the first transistor and the first end of second transistor are electrically connected to bridge rectifier, and the second end of the first transistor is electrically connected to the first end of the second transistor; and a Zener diode, connected between the third end of the first transistor and the second end of the second transistor.
    Type: Application
    Filed: July 31, 2020
    Publication date: April 29, 2021
    Inventors: Sheng-Bo Wang, Chiao Fu, Chang-Hsieh Wu, Jai-Tai Kuo, Chao-Kai Chang, Yao-Zhong Liu, Yi-Ru Shen, Chen-Yu Wang
  • Patent number: 10826067
    Abstract: An energy storage device has an anode, a cathode and an electrolyte membrane, installed in between the anode and the cathode, wherein at least one of the anode, the cathode and the electrolyte membrane is incorporated with a copolymer and the copolymer is grafted to a functional group with ionic conductive function. Therefore, the energy storage device, which utilizes copolymers and electrolyte membranes, has better efficiency of charge/discharge performance; thus the efficiency thereof increases; the lifetime thereof is prolonged effectively.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: November 3, 2020
    Assignee: POLYBATT MATERIALS CO., LTD.
    Inventors: Ping-Lin Kuo, Chih-Hao Tsao, Kuan-Ting Lee, Chien-Ju Wu, Chen-Yu Wang, Chang-Yu Hsu
  • Patent number: 10791601
    Abstract: A light-emitting device has a stabilizing-current circuit, a current source having a high electron mobility transistor, and a light source electrically connected to the stabilizing-current circuit and the current source.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: September 29, 2020
    Assignee: EPISTAR CORPORATION
    Inventors: Chao-Kai Chang, Chen-Yu Wang, Chang-Hseih Wu, Jai-Tai Kuo
  • Publication number: 20190289685
    Abstract: A light-emitting device has a stabilizing-current circuit, a current source having a high electron mobility transistor, and a light source electrically connected to the stabilizing-current circuit and the current source.
    Type: Application
    Filed: March 14, 2019
    Publication date: September 19, 2019
    Inventors: Chao-Kai CHANG, Chen-Yu WANG, Chang-Hseih WU, Jai-Tai KUO
  • Publication number: 20180351179
    Abstract: An energy storage device has an anode, a cathode and an electrolyte membrane, installed in between the anode and the cathode, wherein at least one of the anode, the cathode and the electrolyte membrane is incorporated with a copolymer and the copolymer is grafted to a functional group with ionic conductive function. Therefore, the energy storage device, which utilizes copolymers and electrolyte membranes, has better efficiency of charge/discharge performance; thus the efficiency thereof increases; the lifetime thereof is prolonged effectively.
    Type: Application
    Filed: May 30, 2018
    Publication date: December 6, 2018
    Inventors: PING-LIN KUO, CHIH-HAO TSAO, KUAN-TING LEE, CHIEN-JU WU, CHEN-YU WANG, CHANG-YU HSU
  • Publication number: 20180158078
    Abstract: Embodiments disclosed relate to a computer device and a method for predicting market demand of commodities. The method includes: creating multiple-sources data for each of a plurality of commodities, wherein each of the all multiple-sources data comes from a plurality data sources; storing the all multiple-sources data; extracting a plurality of features from a corresponding one of the all multiple-sources data for each of the commodities to build a feature matrix for each of the data sources; performing a tensor decomposition process on the feature matrices to produce at least one latent feature matrix; and performing a deep learning process on the at least one latent feature matrix to build a prediction model and predicting market demand of each of the commodities according to the prediction model.
    Type: Application
    Filed: December 7, 2016
    Publication date: June 7, 2018
    Inventors: Pei-Yu HSIEH, Hong-Han SHUAI, De-Nian YANG, Yi-Chun CHEN, Meng-Jung SHIH, Chieh-Yu LIAO, Chen-Yu WANG
  • Patent number: D1059315
    Type: Grant
    Filed: April 27, 2023
    Date of Patent: January 28, 2025
    Assignee: GaNrich Semiconductor Corporation
    Inventors: Jia-Tay Kuo, Chen-Yu Wang, Sheng-Bo Wang, Chiao Fu, Yao-Zhong Liu