Abstract: The current disclosure discloses a driving circuit of a liquid crystal display. The driving circuit comprises a P-DAC, an N-DAC, a first input amplifier, a second input amplifier, a first output amplifier, a second output amplifier, a first switching circuit, a second switching circuit and a third switching circuit. The driving circuit is able to provide better brightness compensation for a corresponding pixel electrode and reduce the time needed to drive the corresponding pixel electrode.

Abstract: A half-power buffer amplifier is disclosed. A buffer stage includes a first-half buffer stage and a second-half buffer stage, wherein an output of the first-half buffer stage is controllably fed back to a rail-to-rail differential amplifier, and an output of the second-half buffer stage is controllably fed back to the rail-to-rail differential amplifier. The switch network controls the connection between the outputs of the buffer stage and an output node of the half-power buffer amplifier in a manner such that a same pixel, with respect to different frames, of a display panel is driven by the same rail-to-rail differential amplifier. In one embodiment, the rail-to-rail differential amplifier and the buffer stage comprise half-power transistors operated within and powered by half of a full range spanning from power to ground.

Abstract: An output amplifier includes an amplifier circuit, an output stage circuit, a first switch transistor, and a second switch transistor. The amplifier circuit is used for amplifying an input pixel signal to generate the inverted signal and the non-inverted signal. The output stage circuit has a first output terminal for passing a supply voltage from a supply terminal or passing a ground voltage from a ground terminal to the pixel circuit according to the inverted signal and the non-inverted signal. The first switch transistor passes or blocks the supply voltage according to a high impedance signal, and the second switch transistor passes or blocks the ground voltage according to the inverted high impedance signal.

Abstract: An output amplifier includes an amplifier circuit, a driving stage circuit, an output stage circuit, a first unity gain buffer, and a second unity gain buffer. The amplifier circuit provides an inverted signal and a non-inverted signal, in which the amplifier circuit amplifies an input pixel signal to generate the inverted signal and the non-inverted signal. The output stage circuit passes a supply voltage or a ground voltage to the pixel circuit according to the inverted signal and the non-inverted signal. The driving stage circuit passes the supply voltage or the ground voltage to the pixel circuit. The first unity gain buffer enhances and passes the inverted signal from the amplifier circuit to the driving stage circuit. The second unity gain buffer passes and enhances the non-inverted signal from the amplifier circuit to the driving stage circuit.

Abstract: A source driving circuit adapted to drive a display panel is provided herein. The source driving circuit includes a first output buffer and a second output buffer responsible for enhancing signals with different polarities respectively. As for the first output buffer, the first output buffer includes a first differential input stage, a first output stage and a second output stage. The first output stage includes a first level adjustment circuit and a first self-bias providing circuit. The first level adjustment circuit provides a first level voltage according to input signals received by the first differential input stage, such that the second output stage thereby provides a first charge current and a second charge current to output a first output signal based on the first level voltage. The first self-bias providing circuit provides a first biased voltage associated with one input signal to control the first level adjustment circuit to operate.

Abstract: A ventilator includes a first casing, a second casing, a fan blade and a flow guider. The second casing is connected to the first casing and forms a flow channel between the first casing and the second casing. The fan blade is disposed between the first casing and the second casing. When the fan blade rotates, an air-flow compression zone and an air-flow decompression zone are formed in the flow channel. The flow guider is formed along a boundary line to the air-flow decompression zone, wherein the boundary line is adjacent to the air-flow compression zone and the air-flow decompression zone. With the ventilator, the air pressure of the ventilator is increased and noise can be controlled.

Abstract: A clock driving circuit and a method of driving a plurality of output lines for a PC architecture are disclosed. The clock driving circuit includes a clock generating circuit coupled to an output buffer for the PC having a plurality of output lines connected to a plurality of output loads having output load impedances. The output lines are driven differentially at an output voltage lower than a supply voltage. The circuit includes a voltage node having a voltage node impedance. The voltage node is maintained at substantially the output voltage. The circuit includes a current sinking transistor that sinks current from the voltage node. The current sinking transistor is operated in a linear region characterized by an ohmic resistance determined by the size of the current sinking transistor. The impedance of the voltage node is matched to one of the load impedances by sizing the current sinking transistor.

Abstract: A pixel circuit is disclosed in the present invention, which includes an OLED, a current-driving unit receiving a signal current on a data line during a programming period to provide a corresponding driving current to the OLED, a first switch coupled between the data line and the current-driving unit and turned on during the programming period to conduct the signal current, and a constant current unit providing a constant current on the data line during a pre-programming period and the programming period. The present invention also discloses an apparatus for driving a display, including a scan-driving circuit, a data-driving circuit, and plural constant current units. A method for driving a pixel having an OLED is also disclosed, which includes the steps of receiving a signal current on a data line during a programming period to provide a corresponding driving current to the OLED, and providing a constant current on the data line during a pre-programming period and the programming period.

Abstract: A remote-interaction apparatus comprises a portable electronic device installing a specific software and an interaction unit having an interaction-mode database. The interaction unit can detect a sensory information inputted by a user and find out an interaction information corresponding to the sensory information from the interaction-mode database for transmitting the first interaction information to the portable electronic device by a first communication protocol. And the specific software employs the portable electronic device to transmit the interaction information to another remote-interaction apparatus by a second communication protocol.

Abstract: A half-power buffer amplifier includes a buffer stage having a first-half buffer stage and a second-half buffer stage. An output of the first-half buffer stage is controllably fed back to a rail-to-rail differential amplifier, and an output of the second-half buffer stage is controllably fed back to the rail-to-rail differential amplifier. A switch network controls the connection between the outputs of the buffer stage and an output node of the half-power buffer amplifier in a manner such that a same pixel, with respect to different frames, of a display panel is driven by the same rail-to-rail differential amplifier.

Abstract: A half-power buffer amplifier is disclosed. A buffer stage includes a first-half buffer stage and a second-half buffer stage, wherein an output of the first-half buffer stage is controllably fed back to a rail-to-rail differential amplifier, and an output of the second-half buffer stage is controllably fed back to the rail-to-rail differential amplifier. The switch network controls the connection between the outputs of the buffer stage and an output node of the half-power buffer amplifier in a manner such that a same pixel, with respect to different frames, of a display panel is driven by the same rail-to-rail differential amplifier. In one embodiment, the rail-to-rail differential amplifier and the buffer stage comprise half-power transistors operated within and powered by half of a full range spanning from power to ground.

Abstract: A half-power buffer amplifier includes a buffer stage having a first-half buffer stage and a second-half buffer stage. An output of the first-half buffer stage is controllably fed back to a rail-to-rail differential amplifier, and an output of the second-half buffer stage is controllably fed back to the rail-to-rail differential amplifier. A switch network controls the connection between the outputs of the buffer stage and an output node of the half-power buffer amplifier in a manner such that a same pixel, with respect to different frames, of a display panel is driven by the same rail-to-rail differential amplifier.

Abstract: An output amplifier includes an amplifier circuit, an output stage circuit, a first switch transistor, and a second switch transistor. The amplifier circuit is used for amplifying an input pixel signal to generate the inverted signal and the non-inverted signal. The output stage circuit has a first output terminal for passing a supply voltage from a supply terminal or passing a ground voltage from a ground terminal to the pixel circuit according to the inverted signal and the non-inverted signal. The first switch transistor passes or blocks the supply voltage according to a high impedance signal, and the second switch transistor passes or blocks the ground voltage according to the inverted high impedance signal.

Abstract: An output amplifier includes an amplifier circuit, a driving stage circuit, an output stage circuit, a first unity gain buffer, and a second unity gain buffer. The amplifier circuit provides an inverted signal and a non-inverted signal, in which the amplifier circuit amplifies an input pixel signal to generate the inverted signal and the non-inverted signal. The output stage circuit passes a supply voltage or a ground voltage to the pixel circuit according to the inverted signal and the non-inverted signal. The driving stage circuit passes the supply voltage or the ground voltage to the pixel circuit. The first unity gain buffer enhances and passes the inverted signal from the amplifier circuit to the driving stage circuit. The second unity gain buffer passes and enhances the non-inverted signal from the amplifier circuit to the driving stage circuit.

Abstract: A driver circuit of an AMOLED (active matrix organic light emitting diode) with gamma correction includes a voltage selector, an operational amplifier, a MOS transistor, and a resistive element. The voltage selector selects one of a plurality of gamma voltages. The operational amplifier receives the selected gamma voltage and a feedback signal to generate a control signal. The MOS transistor provides the feedback signal and conducts a current associated with a current type pixel circuit in response to the control signal. The resistive element is coupled to a first voltage end and an inverted input end of the operational amplifier for determining the current with the selected gamma voltage.

Abstract: An output buffer including a first differential input stage, a primary output stage, and a secondary output stage is provided herein. The first differential input stage respectively receives a first and a second input signals via a first and a second input terminals. The primary output stage includes a first and a second output stages. The first output stage provides at least one first level voltage according to the first and the second input signals, and the second output stage controlled by the first level voltage drives an output terminal of the output buffer to a target level. The secondary output stage includes a comparator and a third output stage. The comparator compares the induced currents in the first differential input stage, and thereby generates a control voltage. The third output stage controlled by the control voltage drives the output terminal of the output buffer to the target level.

Abstract: A pixel circuit has a light emitting diode, a driving transistor, a capacitor, a first switch, a second switch, a third switch, and a forth switch. The driving transistor has a drain, coupled to a second end of the light emitting diode. The capacitor is coupled between a gate of the driving transistor and the ground terminal. The third switch is coupled between the source and the gate of the driving transistor. The fourth switch is coupled between the second end of the light emitting diode and a data line. The first switch is off, the second is on, and the third is on during the reset period; the first switch is off, the second is off, and the third is on during the programming period; and the first switch is on, the second is on, and the third is off during the display period.

Abstract: An output buffer including a first differential input stage, a primary output stage, and a secondary output stage is provided herein. The first differential input stage respectively receives a first and a second input signals via a first and a second input terminals. The primary output stage includes a first and a second output stages. The first output stage provides at least one first level voltage according to the first and the second input signals, and the second output stage controlled by the first level voltage drives an output terminal of the output buffer to a target level. The secondary output stage includes a comparator and a third output stage. The comparator compares the induced currents in the first differential input stage, and thereby generates a control voltage. The third output stage controlled by the control voltage drives the output terminal of the output buffer to the target level.

Abstract: A clock driving circuit and a method of driving a plurality of output lines for a PC architecture are disclosed. The clock driving circuit includes a clock generating circuit coupled to an output buffer for the PC having a plurality of output lines connected to a plurality of output loads having output load impedances. The output lines are driven differentially at an output voltage lower than a supply voltage. The circuit includes a voltage node having a voltage node impedance. The voltage node is maintained at substantially the output voltage. The circuit includes a current sinking transistor that sinks current from the voltage node. The current sinking transistor is operated in a linear region characterized by an ohmic resistance determined by the size of the current sinking transistor. The impedance of the voltage node is matched to one of the load impedances by sizing the current sinking transistor.

Abstract: A source driving circuit adapted to drive a display panel is provided herein. The source driving circuit includes a first output buffer and a second output buffer responsible for enhancing signals with different polarities respectively. As for the first output buffer, the first output buffer includes a first differential input stage, a first output stage and a second output stage. The first output stage includes a first level adjustment circuit and a first self-bias providing circuit. The first level adjustment circuit provides a first level voltage according to input signals received by the first differential input stage, such that the second output stage thereby provides a first charge current and a second charge current to output a first output signal based on the first level voltage. The first self-bias providing circuit provides a first biased voltage associated with one input signal to control the first level adjustment circuit to operate.