Patents by Inventor Chen-Yuan Kao

Chen-Yuan Kao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11374127
    Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for weaker and softer dielectric layer. The insert layer may be applied between two weaker dielectric layers or the insert layer may be used with a single layer of dielectric material. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: June 28, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Jen Chang, Chih-Chien Chi, Chen-Yuan Kao, Hung-Wen Su, Kai-Shiang Kuo, Po-Cheng Shih, Jun-Yi Ruan
  • Patent number: 11328952
    Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for surrounding dielectric layers. The insert layer may be applied between two dielectric layers. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: May 10, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng Chou, Chih-Chien Chi, Chung-Chi Ko, Yao-Jen Chang, Chen-Yuan Kao, Kai-Shiang Kuo, Po-Cheng Shih, Tze-Liang Lee, Jun-Yi Ruan
  • Patent number: 11271112
    Abstract: A method for forming a FinFET device structure is provided. The method includes forming a fin structure over a substrate and forming a gate dielectric layer over the fin structure. The method also includes forming a gate electrode layer over the gate dielectric layer and forming a source/drain (S/D) structure adjacent to the gate electrode layer. In addition, the method includes forming an S/D contact structure over the S/D structure. The method also includes forming a first conductive layer in direct with the gate electrode layer. A bottom surface of the first conductive layer is lower than a top surface of the gate dielectric layer. The method further includes forming a second conductive layer over the first conductive layer. The gate electrode layer is electrically connected to the second conductive layer by the first conductive layer.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: March 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Hsun Wang, Kuo-Yi Chao, Rueijer Lin, Chen-Yuan Kao, Mei-Yun Wang
  • Publication number: 20220052168
    Abstract: A method according to the present disclosure includes receiving a workpiece including a gate structure, a first source/drain (S/D) feature, a second S/D feature, a first dielectric layer over the gate structure, the first S/D feature, the second S/D feature, a first S/D contact over the first S/D feature, a second S/D contact over the second S/D feature, a first etch stop layer (ESL) over the first dielectric layer, and a second dielectric layer over the first ESL, forming a S/D contact via through the second dielectric layer and the first ESL to couple to the first S/D contact, forming a gate contact opening through the second dielectric layer, the first ESL, and the first dielectric layer to expose the gate structure, and forming a common rail opening adjoining the gate contact opening to expose the second S/D contact, and forming a common rail contact in the common rail opening.
    Type: Application
    Filed: December 4, 2020
    Publication date: February 17, 2022
    Inventors: Cheng-Wei Chang, Hong-Ming Wu, Chen-Yuan Kao, Li-Hsiang Chao, Yi-Ying Liu
  • Publication number: 20210367043
    Abstract: Vertical interconnect structures and methods of forming are provided. The vertical interconnect structures may be formed by partially filling a first opening through one or more dielectric layers with layers of conductive materials. A second opening is formed in a dielectric layer such that a depth of the first opening after partially filling with the layers of conductive materials is close to a depth of the second opening. The remaining portion of the first opening and the second opening may then be simultaneously filled.
    Type: Application
    Filed: August 3, 2021
    Publication date: November 25, 2021
    Inventors: Po-Yu Huang, Shih-Che Lin, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Rueijer Lin, Chen-Yuan Kao
  • Patent number: 11182524
    Abstract: A fixing device and a fixing method for a clock tree are provided. The fixing method for the clock tree includes: performing a clock signal path tracking operation on a netlist of a circuit according to timing constraint information to obtain a clock tree circuitry structure; identifying a convergency status of the clock tree circuitry structure to find out at least one clock convergence point, and setting one of a plurality of clock signals on the clock convergence point as a selected clock signal; performing a fix point identification operation on the clock tree circuitry structure based on the selected clock signal to obtain a plurality of candidate fix points; and calculating a plurality weighting values of the candidate fix points, obtaining a plurality of selected fixed points according to the weighting values.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: November 23, 2021
    Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Yuan Kao, Hsin-Lung Li, Min-Hsiu Tsai
  • Publication number: 20210341962
    Abstract: An apparatus for adjusting skew of circuit signal and an adjusting method thereof are provided. The adjusting method includes: providing a controller for executing: based on each of a plurality of clock signals, dividing a circuit to generate a plurality of circuit partitions according to a netlist of the circuit; grouping the circuit partitions to respectively generate a plurality of circuit groups; identifying adjacent states of layout areas of the circuit groups; and, adjusting a skew value of each of the circuit groups according to the adjacent states.
    Type: Application
    Filed: July 7, 2020
    Publication date: November 4, 2021
    Applicants: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tse-Wei Wu, Chen-Yuan Kao, Min-Hsiu Tsai
  • Publication number: 20210275464
    Abstract: The present invention provides bio-nanoparticles (BioNPs) for delivering an active agent into hematopoietic stem & progenitor cells (HSPCs). Each BioNP comprises a core and a biological membrane covering the core, which comprises the active agent and a polymer. The biological membrane comprises a phospholipid bilayer and one or more surface proteins of a megakaryocyte (Mk). The active agent remains active after being delivered into the HSPC. Also provided are methods for preparing the BioNPs and uses of the BioNPs for targeted delivery of an active agent into HSPCs and/or treating or preventing a disease or condition in a subject in need thereof.
    Type: Application
    Filed: May 24, 2021
    Publication date: September 9, 2021
    Applicant: University of Delaware
    Inventors: Eleftherios T. Papoutsakis, Emily Day, Erica Winter, Jenna Harris, Chen-Yuan Kao, Samik Das
  • Publication number: 20210272910
    Abstract: A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.
    Type: Application
    Filed: May 3, 2021
    Publication date: September 2, 2021
    Inventors: Wen-Jiun LIU, Chen-Yuan Kao, Hung-Wen Su, Ming-Hsing Tsai, Syun-Ming Jang
  • Patent number: 11107896
    Abstract: Vertical interconnect structures and methods of forming are provided. The vertical interconnect structures may be formed by partially filling a first opening through one or more dielectric layers with layers of conductive materials. A second opening is formed in a dielectric layer such that a depth of the first opening after partially filling with the layers of conductive materials is close to a depth of the second opening. The remaining portion of the first opening and the second opening may then be simultaneously filled.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: August 31, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Yu Huang, Shih-Che Lin, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Rueijer Lin, Chen-Yuan Kao
  • Publication number: 20210257254
    Abstract: A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.
    Type: Application
    Filed: April 19, 2021
    Publication date: August 19, 2021
    Inventors: Yu-Sheng Wang, Chi-Cheng Hung, Chen-Yuan Kao, Yi-Wei Chiu, Liang-Yueh Ou Yang, Yueh-Ching Pai
  • Publication number: 20210167179
    Abstract: A semiconductor structure includes a metal gate structure comprising a gate dielectric layer and a gate electrode, a conductive layer disposed over the metal gate structure, and a contact feature in direct contact with the top portion of the conductive layer, where the conductive layer includes a bottom portion disposed below a top surface of the metal gate structure and a top portion disposed over the top surface of the metal gate structure, and where the top portion laterally extends beyond a sidewall of the bottom portion.
    Type: Application
    Filed: February 15, 2021
    Publication date: June 3, 2021
    Inventors: Chao-Hsun Wang, Yu-Feng Yin, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Chen-Yuan Kao
  • Patent number: 10998269
    Abstract: A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: May 4, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Jiun Liu, Chen-Yuan Kao, Hung-Wen Su, Ming-Hsing Tsai, Syun-Ming Jang
  • Patent number: 10985061
    Abstract: A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: April 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Sheng Wang, Chi-Cheng Hung, Chen-Yuan Kao, Yi-Wei Chiu, Liang-Yueh Ou Yang, Yueh-Ching Pai
  • Publication number: 20210098376
    Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.
    Type: Application
    Filed: August 4, 2020
    Publication date: April 1, 2021
    Inventors: Shih-Che Lin, Po-Yu Huang, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Rueijer Lin, Wei-Jung Lin, Chen-Yuan Kao
  • Publication number: 20210074581
    Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for surrounding dielectric layers. The insert layer may be applied between two dielectric layers. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.
    Type: Application
    Filed: November 16, 2020
    Publication date: March 11, 2021
    Inventors: Chia-Cheng Chou, Chih-Chien Chi, Chung-Chi Ko, Yao-Jen Chang, Chen-Yuan Kao, Kai-Shiang Kuo, Po-Cheng Shih, Tze-Liang Lee, Jun-Yi Ruan
  • Patent number: 10923573
    Abstract: A conductive layer is formed between a metal gate structure, which includes a high-k gate dielectric layer and a gate electrode, and a contact feature. The conductive layer can be selectively deposited on a top surface of the gate electrode or, alternatively, non-selectively formed on the top surface of the gate electrode and the gate dielectric layer by controlling, for example, time of deposition. The conductive layer can have a bottom portion embedded into the gate electrode. The conductive layer and the contact feature can include the same composition, though they may be formed using different deposition techniques.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: February 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Hsun Wang, Yu-Feng Yin, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Chen-Yuan Kao
  • Patent number: 10909291
    Abstract: A method for increasing coverage of a scan test, executed by at least one processor, includes following operations: analyzing a first netlist file and a second netlist file to acquire a change of a circuit structure, in which the first netlist file corresponds to a first scan chain circuitry, and the second netlist file corresponds to a second scan circuitry wherein the second netlist file is generated by processing the first netlist file with executing an engineering change order (ECO); repairing the second scan chain circuitry according to at least one predetermined criterion; evaluating a candidate node of the repaired second scan chain circuitry, to connect a new flip flop circuit generated after executing the ECO to the candidate node; and storing the second netlist file being processed as a third netlist file, to fabricate an integrated circuit.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: February 2, 2021
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Tse-Wei Wu, Yu-Hsun Su, Chen-Yuan Kao, Min-Hsiu Tsai
  • Publication number: 20200388575
    Abstract: A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.
    Type: Application
    Filed: June 22, 2020
    Publication date: December 10, 2020
    Inventors: Wen-Jiun Liu, Chen-Yuan Kao, Hung-Wen Su, Ming-Hsing Tsai, Syun-Ming Jang
  • Publication number: 20200388504
    Abstract: A semiconductor structure includes a metal gate structure including a gate dielectric layer and a gate electrode, the gate electrode including at least a first metal; a conductive layer formed above the gate electrode, the conductive layer including an alloy layer, the alloy layer including at least the first metal and a second metal different from the first metal, the alloy layer extending from a position below a top surface of the metal gate structure to a position above the top surface of the metal gate structure; and a contact feature disposed above the metal gate structure, wherein the contact feature is in direct contact with a top surface of the conductive layer.
    Type: Application
    Filed: August 24, 2020
    Publication date: December 10, 2020
    Inventors: Pang-Sheng Chang, Yu-Feng Yin, Chao-Hsun Wang, Kuo-Yi Chao, Fu-Kai Yang, Mei-Yun Wang, Feng-Yu Chang, Chen-Yuan Kao, Chia-Yang Hung, Chia-Sheng Chang, Shu-Huei Suen, Jyu-Horng Shieh, Sheng-Liang Pan, Jack Kuo-Ping Kuo, Shao-Jyun Wu