Patents by Inventor Chen-Yuan Kao
Chen-Yuan Kao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170200612Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a semiconductor substrate. The dielectric layer has a first recess. The method includes forming a first conductive material layer over an inner wall and a bottom of the first recess. The first conductive material layer is partially filled in the first recess. The method includes performing a reflow process to convert the first conductive material layer into a first conductive layer. The first conductive layer has a second recess in the first recess. The method includes performing an electroplating process or an electroless plating process to form a second conductive layer over the first conductive layer so as to fill the second recess.Type: ApplicationFiled: March 10, 2017Publication date: July 13, 2017Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Rueijer LIN, Chen-Yuan KAO, Chun-Chieh LIN, Huang-Yi HUANG
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Publication number: 20170133324Abstract: A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.Type: ApplicationFiled: January 9, 2017Publication date: May 11, 2017Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Jiun LIU, Chen-Yuan KAO, Hung-Wen SU, Ming-Hsing TSAI, Syun-Ming JANG
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Patent number: 9632498Abstract: A computer-implemented system and method of compensating for filling material losses in a semiconductor process. The computer-implemented method includes determining using a computer a pattern density difference between a first circuit pattern above a semiconductor substrate and a second circuit pattern adjacent to the first pattern. A dummy pattern is inserted between the first pattern and the second pattern so as to compensate for an estimated loss of filling material induced during electrochemical plating by the pattern density difference exceeding a threshold pattern density difference.Type: GrantFiled: April 25, 2013Date of Patent: April 25, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Yi Chang, Liang-Yueh Ou Yang, Chen-Yuan Kao, Hung-Wen Su
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Publication number: 20170081775Abstract: A method of plating a metal layer on a work piece includes exposing a surface of the work piece to a plating solution, and supplying a first voltage at a negative end of a power supply source to an edge portion of the work piece. A second voltage is supplied to an inner portion of the work piece, wherein the inner portion is closer to a center of the work piece than the edge portion. A positive end of the power supply source is connected to a metal plate, wherein the metal plate and the work piece are spaced apart from each other by, and are in contact with, the plating solution.Type: ApplicationFiled: December 1, 2016Publication date: March 23, 2017Inventors: Chen-Yuan Kao, Hung-Wen Su, Minghsing Tsai
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Patent number: 9601430Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a dielectric layer positioned on the semiconductor substrate. The dielectric layer has a first recess. The semiconductor device structure includes a conductive structure filling the first recess. The conductive structure includes a first conductive layer and a second conductive layer. The first conductive layer is positioned over an inner wall and a bottom of the first recess. The first conductive layer has a second recess in the first recess. The second conductive layer fills the second recess. The first conductive layer and the second conductive layer include cobalt. The second conductive layer further includes at least one of sulfur, chlorine, boron, phosphorus, or nitrogen.Type: GrantFiled: October 2, 2014Date of Patent: March 21, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Rueijer Lin, Chen-Yuan Kao, Chun-Chieh Lin, Huang-Yi Huang
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Publication number: 20170058262Abstract: Applications in transfusion medicine requiring platelets, and hematopoietic stem-cell transplantations require either platelets or enhancement of in vivo platelet biogenesis. Gene therapy applications of hematopoietic stem and progenitor cells (HSPCs) require effective and specific modification of HSPCs by DNA, RNA or other biological molecules. Here we disclose methods for the generation, and modification of megakaryocytic microparticles (MkMPs) or microvesicles, that can be used in the aforementioned transfusion and transplantation medicine applications and in gene therapy applications involving hematopoietic stem cells. The biological effects of modified or unmodified MkMPs have never been previously disclosed and thus, this invention claims all biological applications of MkMPs in in vivo therapeutic applications or ex vivo applications to produce various cells and cell parts, modify various target cells or deliver molecules including drugs to HSPCs and related cells.Type: ApplicationFiled: May 18, 2015Publication date: March 2, 2017Inventors: Eleftherios Papoutsakis, Chen-Yuan Kao, Jinlin Jiang
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Patent number: 9564398Abstract: A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.Type: GrantFiled: March 15, 2013Date of Patent: February 7, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Jiun Liu, Chen-Yuan Kao, Hung-Wen Su, Mingh-Hsing Tsai, Syun-Ming Jang
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Patent number: 9518334Abstract: A method of plating a metal layer on a work piece includes exposing a surface of the work piece to a plating solution, and supplying a first voltage at a negative end of a power supply source to an edge portion of the work piece. A second voltage is supplied to an inner portion of the work piece, wherein the inner portion is closer to a center of the work piece than the edge portion. A positive end of the power supply source is connected to a metal plate, wherein the metal plate and the work piece are spaced apart from each other by, and are in contact with, the plating solution.Type: GrantFiled: April 26, 2013Date of Patent: December 13, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Yuan Kao, Hung-Wen Su, Minghsing Tsai
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Patent number: 9476135Abstract: The present disclosure relates to an electro-chemical plating (ECP) process which utilizes a dummy electrode as a cathode to perform plating for sustained idle times to mitigate additive dissociation. The dummy electrode also allows for localized plating function to improve product gapfill, and decrease wafer non-uniformity. A wide range of electroplating recipes may be applied with this strategy, comprising current plating up to approximately 200 Amps, localized plating with a resolution of approximately 1 mm, and reverse plating to remove material from the dummy electrode accumulated during the dummy plating process and replenish ionic material within the electroplating solution.Type: GrantFiled: April 9, 2013Date of Patent: October 25, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Yi Chang, Liang-Yueh Ou Yang, Chen-Yuan Kao, Hung-Wen Su
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Publication number: 20160099216Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a dielectric layer positioned on the semiconductor substrate. The dielectric layer has a first recess. The semiconductor device structure includes a conductive structure filling the first recess. The conductive structure includes a first conductive layer and a second conductive layer. The first conductive layer is positioned over an inner wall and a bottom of the first recess. The first conductive layer has a second recess in the first recess. The second conductive layer fills the second recess. The first conductive layer and the second conductive layer include cobalt. The second conductive layer further includes at least one of sulfur, chlorine, boron, phosphorus, or nitrogen.Type: ApplicationFiled: October 2, 2014Publication date: April 7, 2016Applicant: Taiwan Semiconductor Manufacturing Co., LtdInventors: Rueijer LIN, Chen-Yuan KAO, Chun-Chieh LIN, Huang-Yi HUANG
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Publication number: 20160064332Abstract: A method of forming a metal layer may include forming an opening in a substrate; forming a liner over sidewalls of the opening; filling the opening with a first metal; etching a top surface of the first metal to form a recessed top surface below a top surface of the substrate; and exposing the recessed top surface of the first metal to a solution, the solution containing a second metal different from the first metal, the exposing causing the recessed top surface of the first metal to attract the second metal to form a cap layer over the recessed top surface of the first metal.Type: ApplicationFiled: November 10, 2015Publication date: March 3, 2016Inventors: Chen-Yuan Kao, Hung-Wen Su, Chih-Yi Chang, Liang-Yueh Ou Yang
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Patent number: 9209073Abstract: Presented herein is a method for electrolessly forming a metal cap in a via opening, comprising bringing a via into contact with metal solution, the via disposed in an opening in a substrate, and forming a metal cap in the opening and in contact with the via, the metal cap formed by an electroless chemical reaction. A metal solution may be applied to the via to form the metal cap. The metal solution may comprises at least cobalt and the cap may comprise at least cobalt, and may optionally further comprise tungsten, and wherein the forming the cap comprises forming the cap to further comprise at least tungsten. The metal solution may further comprise at least hypophosphite or dimethylaminoborane.Type: GrantFiled: March 25, 2013Date of Patent: December 8, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Liang-Yueh Ou Yang, Chih-Yi Chang, Chen-Yuan Kao, Hung-Wen Su
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Publication number: 20140262800Abstract: Presented herein is a method of processing a device, comprising providing an electroplating bath having a leveler, the leveler having a total nitrogen-to-total carbon (TN/TOC) ratio of about 15% or less, bringing a substrate into contact with the electroplating bath, the substrate having a recess formed therein and electroplating the substrate to create a feature substantially free of voids in the substrate recess. Electroplating the substrate is performed for a time period about as long as an electrical response peak of the leveler, and optionally for at least 30 seconds. The leveler may optionally have at least one ingredient free of nitrogen and having a leveling functionality. One ingredient may be a benzene ring free of nitrogen. The leveler TN/TOC ratio is between about 3% and about 15%.Type: ApplicationFiled: March 27, 2013Publication date: September 18, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Yuan Kao, Hung-Wen Su, Minghsing Tsai
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Publication number: 20140262797Abstract: The present disclosure relates to an electro-chemical plating (ECP) process which utilizes a dummy electrode as a cathode to perform plating for sustained idle times to mitigate additive dissociation. The dummy electrode also allows for localized plating function to improve product gapfill, and decrease wafer non-uniformity. A wide range of electroplating recipes may be applied with this strategy, comprising current plating up to approximately 200 Amps, localized plating with a resolution of approximately 1 mm, and reverse plating to remove material from the dummy electrode accumulated during the dummy plating process and replenish ionic material within the electroplating solution.Type: ApplicationFiled: April 9, 2013Publication date: September 18, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Yi Chang, Liang-Yueh Ou Yang, Chen-Yuan Kao, Hung-Wen Su
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Publication number: 20140264866Abstract: A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Inventors: Wen-Jiun Liu, Chen-Yuan Kao, Hung-Wen Su, Mingh-Hsing Tsai, Syun-Ming Jang
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Publication number: 20140277681Abstract: A computer-implemented system and method of compensating for filling material losses in a semiconductor process. The computer-implemented method includes determining using a computer a pattern density difference between a first circuit pattern above a semiconductor substrate and a second circuit pattern adjacent to the first pattern. A dummy pattern is inserted between the first pattern and the second pattern so as to compensate for an estimated loss of filling material induced during electrochemical plating by the pattern density difference exceeding a threshold pattern density difference.Type: ApplicationFiled: April 25, 2013Publication date: September 18, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Yi CHANG, Liang-Yueh Ou YANG, Chen-Yuan KAO, Hung-Wen SU
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Publication number: 20140251814Abstract: A method of plating a metal layer on a work piece includes exposing a surface of the work piece to a plating solution, and supplying a first voltage at a negative end of a power supply source to an edge portion of the work piece. A second voltage is supplied to an inner portion of the work piece, wherein the inner portion is closer to a center of the work piece than the edge portion. A positive end of the power supply source is connected to a metal plate, wherein the metal plate and the work piece are spaced apart from each other by, and are in contact with, the plating solution.Type: ApplicationFiled: April 26, 2013Publication date: September 11, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Yuan Kao, Hung-Wen Su, Minghsing Tsai
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Publication number: 20080290175Abstract: A layer-built body having hidden barcodes and figures thereof is disclosed in the invention, so as to allow barcode scanning devices to read the barcodes, the layer-built body comprising: a lenticular lens sheet divided into a first surface and a second surface, and the first surface has a plurality of convex lens-shaped optical structures disposed thereon; a patterned layer printed with trademarks or figures, and divided into a plurality of striped images; and at least a barcode layer printed with information about barcodes and divided into a plurality of striped images.Type: ApplicationFiled: March 24, 2008Publication date: November 27, 2008Applicants: Alfred Lean-Foo CHEN, Shuo-Fang LIU, Chen-Yuan KAOInventors: Alfred Lean-Foo Chen, Shuo-Fang Liu, Yuei-An Liou, Hsin-His Lai, Meng-Hsuan Lee, Ying-Hsiu Chen, Chen-Yuan Kao, Chang-Ching Chien, Jung-Hao Chi, Cheng-Yu Lu