Abstract: A semiconductor device including a capacitor, with a memory film isolating a first electrode from a contact, formed over a transistor and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a gate stack over a semiconductor substrate; a capacitor over the gate stack, the capacitor including a first electrode extending along a top surface of the gate stack, the first electrode being U-shaped; a first ferroelectric layer over the first electrode; and a second electrode over the first ferroelectric layer, a top surface of the second electrode being level with a top surface of the first ferroelectric layer, and the top surface of the first ferroelectric layer and the top surface of the second electrode being disposed further from the semiconductor substrate than a topmost surface of the first electrode.

Abstract: A semiconductor structure includes a first cell, a second cell, a first bit line, a first source line, a second bit line, and a second source line. The first cell includes a first source structure and a first drain structure. The second cell includes a second source structure and a second drain structure. The first bit line is coupled to the first drain structure, the first source line is coupled to the first source structure, the second bit line is coupled to the second drain structure, and the second source line is coupled to the second source structure. The first source line and the first bit line are alternately arranged, and the second source line and the second bit line are alternately arranged. A distance between the first source line and the first bit line is similar to a distance between the second source line and the second bit line.

Abstract: A semiconductor memory structure includes a first cell including a first source structure and a first drain structure, a second cell including a second source structure and a second drain structure, a first bit line, a first source line, a second bit line and a second source line. The first source line is coupled to the first source structure. The first bit line is coupled to the first drain structure. The second source line is coupled to the second source structure. The second bit line is coupled to the second drain structure. The first source line and the first bit line are in a first common layer. The second bit line and the second source line are in a second common layer. A distance between the first source line and the first bit line is similar to a distance between the second source line and the second bit line.

Abstract: A power battery heating system of an electric vehicle including: a heating module configured to heat the power battery of the electric vehicle; a solar sunroof; and a sunroof control unit configured to control the operation of the heating module and the electric energy output of the solar sunroof; wherein the heating system is configured to start a power battery heating operation based on the solar sunroof when the power battery is not in a high voltage output state and the temperature of the power battery is lower than a temperature threshold, the power battery heating operation including: controlling the solar sunroof to output electric energy to the heating module such that the heating module performs the heating of the power battery using the electric energy from the solar sunroof.

Abstract: The present disclosure provides a polypeptide capable of dissolving protein aggregates. Also provided is a method of treating a neurodegeneration disease using the polypeptide.

Abstract: The present disclosure provides a polypeptide capable of dissolving protein aggregates. Also provided is a method of treating a neurodegeneration disease using the polypeptide.

Abstract: An electrode material for an energy storage device including a covalent organic framework includes a plurality of aromatic moieties each linked by at least one thioether linkage. An anode including said electrode material, and an energy storage device having said anode.

Abstract: A covalent organic framework includes a plurality of aromatic moieties each linked by at least one thioether linkage, and its preparation method. An energy storage device includes a cell with an electrode including the covalent organic framework.

Abstract: A semiconductor memory structure includes a first cell including a first source structure and a first drain structure, a second cell including a second source structure and a second drain structure, a first bit line, a first source line, a second bit line and a second source line. The first source line is coupled to the first source structure. The first bit line is coupled to the first drain structure. The second source line is coupled to the second source structure. The second bit line is coupled to the second drain structure. The first source line and the first bit line are in a first common layer. The second bit line and the second source line are in a second common layer. A distance between the first source line and the first bit line is similar to a distance between the second source line and the second bit line.

Abstract: A device includes a first transistor over a substrate, a second transistor disposed over the first transistor, and a memory element disposed over the second transistor. The second transistor includes a channel layer, a gate dielectric layer surrounding a sidewall of the channel layer, and a gate electrode surrounding a sidewall of the gate dielectric layer.

Abstract: A device includes a first transistor over a substrate, a second transistor disposed over the first transistor, and a memory element disposed over the second transistor. The second transistor includes a channel layer, a gate dielectric layer surrounding a sidewall of the channel layer, and a gate electrode surrounding a sidewall of the gate dielectric layer.

Abstract: A semiconductor memory structure includes a first cell, a second cell, a first bit line, a first source line, a second bit line and a second source line. The first cell includes a first source structure and a first drain structure, and the second cell includes a second source structure and a second drain structure. The first source line is coupled to the first source structure, and the first bit line is coupled to the first drain structure. The second source line is coupled to the second source structure, and the second bit line is coupled to the second drain structure. A distance between the first source line and the second bit line, a distance between the second bit line and the second source line, and a distance between the second source line and the first bit line are similar.

Abstract: A semiconductor device including a capacitor, with a memory film isolating a first electrode from a contact, formed over a transistor and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a gate stack over a semiconductor substrate; a capacitor over the gate stack, the capacitor including a first electrode extending along a top surface of the gate stack, the first electrode being U-shaped; a first ferroelectric layer over the first electrode; and a second electrode over the first ferroelectric layer, a top surface of the second electrode being level with a top surface of the first ferroelectric layer, and the top surface of the first ferroelectric layer and the top surface of the second electrode being disposed further from the semiconductor substrate than a topmost surface of the first electrode.

Abstract: A semiconductor device including a capacitor, with a memory film isolating a first electrode from a contact, formed over a transistor and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a gate stack over a semiconductor substrate; a capacitor over the gate stack, the capacitor including a first electrode extending along a top surface of the gate stack, the first electrode being U-shaped; a first ferroelectric layer over the first electrode; and a second electrode over the first ferroelectric layer, a top surface of the second electrode being level with a top surface of the first ferroelectric layer, and the top surface of the first ferroelectric layer and the top surface of the second electrode being disposed further from the semiconductor substrate than a topmost surface of the first electrode.

Abstract: The present disclosure provides a polypeptide capable of dissolving protein aggregates. Also provided is a method of treating a neurodegeneration disease using the polypeptide.

Abstract: A semiconductor device including a capacitor, with a memory film isolating a first electrode from a contact, formed over a transistor and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a gate stack over a semiconductor substrate; a capacitor over the gate stack, the capacitor including a first electrode extending along a top surface of the gate stack, the first electrode being U-shaped; a first ferroelectric layer over the first electrode; and a second electrode over the first ferroelectric layer, a top surface of the second electrode being level with a top surface of the first ferroelectric layer, and the top surface of the first ferroelectric layer and the top surface of the second electrode being disposed further from the semiconductor substrate than a topmost surface of the first electrode.

Abstract: A semiconductor memory structure includes a first cell, a second cell, a first bit line, a first source line, a second bit line and a second source line. The first cell includes a first source structure and a first drain structure, and the second cell includes a second source structure and a second drain structure. The first source line is coupled to the first source structure, and the first bit line is coupled to the first drain structure. The second source line is coupled to the second source structure, and the second bit line is coupled to the second drain structure. A distance between the first source line and the second bit line, a distance between the second bit line and the second source line, and a distance between the second source line and the first bit line are similar.

Abstract: Provided are a method of producing a modified T cell comprising introducing into a precursor T cell a first nucleic acid encoding a Nef protein, wherein the Nef protein upon expression results in down-modulation of the endogenous T cell receptor (TCR) in the modified T cell, wherein the modified T cell furthermore expresses a functional exogenous receptor, such as an engineered TCR (e.g., chimeric TCR), T cell antigen coupler (TAC), TAC-like chimeric receptor, or a chimeric antigen receptor (CAR), the modified cell obtained by the method and the pharmaceutical composition comprising the modified T cell. Also provided is a non-naturally occurring Nef protein comprising one or more mutations.

Abstract: A device includes a first transistor over a substrate, a second transistor disposed over the first transistor, and a memory element disposed over the second transistor. The second transistor includes a channel layer, a gate dielectric layer surrounding a sidewall of the channel layer, and a gate electrode surrounding a sidewall of the gate dielectric layer.

Abstract: A power battery heating system of an electric vehicle including: a heating module configured to heat the power battery of the electric vehicle; a solar sunroof; and a sunroof control unit configured to control the operation of the heating module and the electric energy output of the solar sunroof; wherein the heating system is configured to start a power battery heating operation based on the solar sunroof when the power battery is not in a high voltage output state and the temperature of the power battery is lower than a temperature threshold, the power battery heating operation including: controlling the solar sunroof to output electric energy to the heating module such that the heating module performs the heating of the power battery using the electric energy from the solar sunroof.