Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a first isolation structure, and a second isolation structure. The substrate has a first region and a second region. The first isolation structure is disposed within the first region of the substrate. The first isolation structure includes a first dielectric layer and a first nitridation layer disposed between the substrate and the first dielectric layer. The second isolation structure is disposed within the second region of the substrate.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes providing a substrate. The method also includes forming a first trench within the substrate. The method further includes forming a first nitridation layer within the first trench. In addition, the method includes forming a first isolation layer on the first nitridation layer to form a first isolation structure.

Abstract: The present disclosure provides a method of manufacturing a semiconductor device, The method includes providing a substrate, forming a metallization layer on the substrate, forming an upper dielectric layer over the metallization layer, forming a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer penetrating the upper dielectric layer and the metallization layer, wherein the first sacrificial layer is aligned with the third sacrificial layer along a first axis, and the second sacrificial layer is free from overlapping the first sacrificial layer and the third sacrificial layer along the first axis, forming a width controlling structure between the first sacrificial layer and the third sacrificial layer, wherein the width controlling structure defines a recess exposing the upper dielectric layer, forming a protective layer within the recess, removing the width controlling structure to expose a portion of the metallization layer.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes: providing a substrate; forming a metallization layer on the substrate; forming an upper dielectric layer over the s metallization layer; forming a first sacrificial layer and a second sacrificial layer, each of which penetrates the upper dielectric layer and the metallization layer; removing the upper dielectric layer; forming a width controlling structure between the first sacrificial layer and the second sacrificial layer, wherein the width controlling structure defines a recess exposing the metallization layer; forming a protective layer within the recess of the width controlling structure; removing the width controlling structure to expose a portion of the metallization layer; and patterning the metallization layer to form a word line between the first sacrificial layer and the second sacrificial layer.

Abstract: The present disclosure provides a method of preparing active areas. The method includes the operations of: receiving a substrate having an oxide layer, a nitride layer, and a silicon layer thereon; forming a patterned photoresist layer on the silicon layer; depositing a mask layer to cover a contour of the patterned photoresist layer; coating a carbon layer on the mask layer; etching the carbon layer, the mask layer, and the silicon layer to expose a top surface of the nitride layer; forming a plurality of opens in the oxide layer to expose a top surface of the substrate; and growing an epitaxial layer from the top surface of the substrate in the plurality of opens to form the active areas.

Abstract: The present disclosure provides a method of preparing active areas. The method includes the operations of: receiving a substrate having an oxide layer, a nitride layer, and a silicon layer thereon; forming a patterned photoresist layer on the silicon layer; depositing a mask layer to cover a contour of the patterned photoresist layer; coating a carbon layer on the mask layer; etching the carbon layer, the mask layer, and the silicon layer to expose a top surface of the nitride layer; forming a plurality of opens in the oxide layer to expose a top surface of the substrate; and growing an epitaxial layer from the top surface of the substrate in the plurality of opens to form the active areas.

Abstract: A block erase method for a flash memory is provided. The block erase method is to perform block erase on a block with a predetermined block size. The block erase method includes: performing an erase verification on bytes byte-by-byte in the block when performing the block erase; checking an erase step of the byte when the byte does not pass the erase verification; when the erase step of the byte exceeds a predetermined threshold value, performing the block erase with a partitioned block smaller than the predetermined block size, and returning to an erase verification stage to perform the erase verification; and when the erase step of the bytes does not exceed the predetermined threshold value, continuing to perform the block erase with the predetermined block size, and returning to the erasure verification stage to continue to perform the erase verification.

Abstract: A detection method of a three-dimensional touch module includes: step S1, providing an input signal to a transmitting electrode layer; step S2, outputting a first output signal and transmitting the first output signal to a control module by a two-dimensional inputting assembly, and outputting a second output signal and transmitting the second output signal to the control module by a pressure sensing assembly; and step S3, determining, by the control module, a touch position according to the first output signal and a pressure value according to the second output signal. A three-dimensional touch module includes: a cover plate; a two-dimensional inputting assembly disposed under the cover plate and configured to output a first output signal; a pressure sensing assembly disposed under the cover plate and configured to output a second output signal; and a transmitting electrode layer disposed between the two-dimensional inputting assembly and the pressure sensing assembly.

Abstract: A method for preparing a semiconductor device structure is provided. The method includes forming a target layer over a semiconductor substrate; forming an energy-sensitive layer over the target layer; performing a first energy treating process to form a plurality of first treated portions in the energy-sensitive layer; performing a second energy treating process to form a plurality of second treated portions in the energy-sensitive layer; removing the first treated portions and the second treated portions to respectively form a plurality of first openings and a plurality of second openings; transferring the first openings and the second openings into the target layer to respectively form a plurality of third openings and a plurality of fourth openings; and transferring the third openings and the fourth openings into the semiconductor substrate to respectively form a plurality of fifth openings and a plurality of sixth openings.

Abstract: A semiconductor structure includes an isolation structure disposed in a semiconductor substrate; a gate electrode and a resistor electrode disposed in the semiconductor substrate, wherein the isolation structure is disposed between the gate electrode and the resistor electrode, and the isolation structure is closer to the resistor electrode than the gate electrode. A source/drain (S/D) region is disposed in the semiconductor substrate and between the gate electrode and the isolation structure, wherein the S/D region is electrically connected to the resistor electrode. A conductive structure is disposed in the semiconductor structure and over the isolation structure, wherein the S/D region is electrically connected to the resistor electrode through the conductive structure.

Abstract: The disclosure provides a floating touch display device which includes a capacitive touch panel, a display device, an interval layer, and an optical-lens structure. The capacitive touch panel is configured to provide a floating touch surface at a floating height above a first surface. The display device includes a second surface, and the display device is configured to provide a display image from the second surface. The optical-lens structure is disposed between the capacitive touch panel and the display device. The interval layer is disposed between the second surface and the optical-lens structure, and a first optical distance is between the second surface and the optical-lens structure. The optical-lens structure is configured to image the display image on the floating touch surface at a second optical distance, and the first optical distance is equal to the second optical distance.

Abstract: A common mode filter includes a magnetic core, a first wire wound around the magnetic core and comprising N turns, and a second wire wound around the magnetic core and comprising N turns, N being an integer exceeding 1. An (S+1)th turn of the first wire is stacked on an inner turn of the first wire and an inner turn of the second wire, S being a positive integer less than (N?1).

Abstract: The present disclosure relates to a semiconductor device and a method for forming a semiconductor device with a graphene conductive structure. The semiconductor device includes a first gate structure disposed over a semiconductor substrate, and a first source/drain region disposed in the semiconductor substrate and adjacent to the first gate structure. The semiconductor device also includes a first silicide layer disposed in the semiconductor substrate and over the first source/drain region, and a graphene conductive structure disposed over the first silicide layer. The semiconductor device further includes a first dielectric layer covering the first gate structure, and a second dielectric layer disposed over the first dielectric layer. The graphene conductive structure is surrounded by the first dielectric layer and the second dielectric layer.

Abstract: A hydrodynamic bearing structure is provided. The hydrodynamic bearing structure includes a bearing body, a shaft hole, at least one oil guide groove assembly, at least one air escape unit, and a recess. The shaft hole is formed in the bearing body and penetrates through the bearing body to two ends of the bearing body. The oil guide groove assembly is formed on an inner wall of the shaft hole. The air escape unit is disposed on an outer wall of the bearing body, and has a groove or a tangent plane. The recess is formed at one of the two ends (e.g., a bottom end or a top end) of the bearing body. The recess is spatially communicated with the air escape unit so that an exhaust passage is formed between an axis of the bearing structure and the air escape unit.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure. The method includes providing a substrate defined with a peripheral region and an array area at least partially surrounded by the peripheral region; disposing an insulating layer over the substrate; disposing a capping layer over the insulating layer; disposing a hardmask stack on the capping layer; patterning the hardmask stack; removing portions of the capping layer exposed through the hardmask stack; removing portions of the insulating layer exposed through the hardmask stack; removing portions of the substrate exposed through the capping layer and the insulating layer to form a plurality of fins in the array area and a first elongated member at least partially surrounding the plurality of fins; removing the hardmask stack; and forming an isolation over the substrate and surrounding the plurality of fins and the first elongated member.

Abstract: A hydrodynamic bearing structure is provided. The hydrodynamic bearing structure includes a bearing body, a shaft hole, at least one oil guide groove assembly, at least one air escape unit, and a recess. The shaft hole is formed in the bearing body and penetrates through the bearing body to two ends of the bearing body. The oil guide groove assembly is formed on an inner wall of the shaft hole. The air escape unit is disposed on an outer wall of the bearing body, and has a groove or a tangent plane. The recess is formed at one of the two ends (e.g., a bottom end or a top end) of the bearing body. The recess is spatially communicated with the air escape unit so that an exhaust passage is formed between an axis of the bearing structure and the air escape unit.

Abstract: The present disclosure provides a semiconductor device with an interconnect part and a method for preparing the semiconductor device. The semiconductor device comprises a device substrate and an interconnect part disposed over the device substrate. The interconnect part includes a lower redistribution layer electrically connected to the backside contact, and an upper redistribution layer disposed over the lower redistribution layer. The interconnect part also includes an interconnect frame disposed between and electrically connected to the lower redistribution layer and the upper redistribution layer. The interconnect part further includes a passivation structure surrounding the interconnect frame.

Abstract: A three-dimensional sensing module includes a touch pressure sensing structure. The touch pressure sensing structure includes a first functional spacer layer, a first light-transmitting electrode layer coated on the first functional spacer layer, a second functional spacer layer coated on the first light-transmitting electrode layer, a second light-transmitting electrode layer coated on the second functional spacer layer, and a third functional spacer layer coated on the second light-transmitting electrode layer. Resistivities of the first, second, and third functional spacer layers are greater than resistivities of the first and second light-transmitting electrode layers.

Abstract: A method of forming a semiconductor structure includes following steps. A semiconductor material structure is formed over a substrate. A first pad layer is formed over the semiconductor material structure. The first pad layer and the semiconductor material structure are etched to form a trench. An oxidation process is performed on a sidewall of the semiconductor material structure to form a first oxide structure on the sidewall of the semiconductor material structure. A second oxide structure is formed in the trench.

Abstract: The present disclosure is related to a method of forming a pattern, including the steps of: providing a structure including a substrate and a target layer, in which the target layer is disposed on the substrate, and the target layer includes a central area and a periphery area; forming a plurality of core patterns and a linear spacer pattern on the central area, in which a width of the linear spacer pattern is wider than 50 nm; covering a photoresist on the periphery area; removing a portion of the central area not covered by the plurality of core patterns and not covered by the linear spacer pattern to form a pattern in the central area, and removing the photoresist, the linear spacer pattern and the plurality of core patterns to expose the pattern.