Abstract: Provided is a semiconductor device including a substrate, an interconnect structure, a first passivation layer, a stress buffer layer, a pad structure, and a second passivation layer. The interconnect structure is disposed on the substrate. The first passivation layer and the stress buffer layer are disposed on the interconnect structure. The pad structure includes: a lower portion embedded in the first passivation layer and the stress buffer layer, and laterally wrapped by the first passivation layer and the stress buffer layer; and an upper portion on the lower portion. The upper portion has a periphery laterally offset outward from a periphery of the lower portion, so that a bottom surface of the upper portion contacts a top surface of the stress buffer layer. The second passivation layer is disposed on the stress buffer layer and laterally wraps the upper portion of the upper portion of the pad structure.

Abstract: A method is provided for managing over-the-top delivery of content through a plurality of content delivery networks (CDN). The method provided works transparently with standard HTTP servers supporting an initial request for content from a client to a first preferred CDN. If the first CDN does not have the content, the method includes provisions for the first CDN to acquire the content from a second CDN, or for the client to request the content from a second CDN directly. A system is also specified for implementing a client and server infrastructure in accordance with the provisions of the method.

Abstract: An embedded flash memory device includes a gate stack, which includes a bottom dielectric layer extending into a recess in a semiconductor substrate, and a charge storage layer over the bottom dielectric layer. The charge storage layer includes a portion in the recess. The gate stack further includes a top dielectric layer over the charge storage layer, and a metal gate over the top dielectric layer. Source and drain regions are in the semiconductor substrate, and are on opposite sides of the gate stack.

Abstract: A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound.

Abstract: A lithography system includes a collector having a mirror surface, a laser generator aiming at an excitation zone in front of the mirror surface of the collector, a droplet generator, and a droplet deflector operative to apply a force at a position between the droplet generator and the excitation zone.

Abstract: Systems and method are provided for a memory circuit that includes a bit cell responsive to a bit line signal line and a bit line bar signal line configured to store a bit of data. A pre-charge circuit is configured to charge one of the bit line and bit line bar signal lines prior to a read operation, where the pre-charge circuit includes a first pre-charge component and a second pre-charge component, the first and second pre-charge components being individually controllable for charging the bit line and bit line bar signal lines.

Abstract: Various embodiments of the present disclosure are directed towards a method to embed planar field-effect transistor (FETs) with fin field-effect transistors (finFETs). A semiconductor substrate is patterned to define a mesa and a fin. A trench isolation structure is formed overlying the semiconductor substrate and surrounding the mesa and the fin. A first gate dielectric layer is formed on the mesa, but not the fin. The trench isolation structure recessed around the fin, but not the mesa, after the forming the first gate dielectric layer. A second gate dielectric layer is deposited overlying the first gate dielectric layer at the mesa and further overlying the fin. A first gate electrode is formed overlying the first and second gate dielectric layers at the mesa and partially defining a planar FET. A second gate electrode is formed overlying the second gate dielectric layer at the fin and partially defining a finFET.

Abstract: The semiconductor structure includes a first die structure including a first substrate, a first bonding dielectric disposed over the first substrate, and a first bonding pad surrounded by the first bonding dielectric; a second die structure including a second substrate, an isolation member extending into the second substrate, a second bonding dielectric bonded with the first bonding dielectric, and a second bonding pad surrounded by the second bonding dielectric and bonded with the first bonding pad; a dielectric member disposed over the second die structure; a conductive via extending through the dielectric member, the second substrate and the isolation member; and a conductive member disposed over the dielectric member and at least partially in contact with the conductive via, wherein a first interface between the conductive via and the conductive member is substantially coplanar with a second interface between the conductive member and the dielectric member.

Abstract: A method for fabricating a semiconductor device includes receiving a silicon substrate having an isolation feature disposed on the substrate and a well adjacent the isolation feature, wherein the well includes a first dopant. The method also includes etching a recess to remove a portion of the well and epitaxially growing a silicon layer (EPI layer) in the recess to form a channel, wherein the channel includes a second dopant. The method also includes forming a barrier layer between the well and the EPI layer, the barrier layer including at least one of either silicon carbon or silicon oxide. The barrier layer can be formed either before or after the channel. The method further includes forming a gate electrode disposed over the channel and forming a source and drain in the well.

Abstract: A tool includes a barrel, a guiding wire, and an electrically conductive member. The barrel is made of electrically conductive material. The guiding wire is disposed in the barrel. The barrel and the guiding wire are directly or indirectly connected to two opposite electrodes of a power source. The electrically conductive member is connected to an outer periphery of the guiding wire and is electrically connected to the guiding wire. The electrically conductive member is disposed between the barrel and the guiding wire and is spaced from the barrel. When the power source is activated, an electric arc is generated between the electrically conductive member and the barrel.

Abstract: Some implementations described herein provide an exposure tool. The exposure tool includes a reticle deformation detector and one or more processors configured to obtain, via the reticle deformation detector, reticle deformation information associated with a reticle during a scanning process for scanning multiple fields of a wafer. The one or more processors determine, based on the reticle deformation information, a deformation of the reticle at multiple times during the scanning process, and perform, based on the deformation of the reticle at the multiple times, one or more adjustments of one or more components of the exposure tool during the scanning process.

Abstract: A semiconductor device includes a substrate, a first well, a second well, a metal gate, a poly gate, a source region, and a drain region. The first well and the second well are within the substrate. The metal gate is partially over the first well. The poly gate is over the second well. The poly gate is separated from the metal gate, and a width ratio of the poly gate to the metal gate is in a range from about 0.1 to about 0.2. The source region and the drain region are respectively within the first well and the second well.

Abstract: The present application discloses a method for locating an open circuit failure point of a test structure, which includes the following steps: step 1: providing a sample formed with a test structure, a first metal layer pattern and a second metal layer pattern of the test structure forming a series resistor structure through each via; step 2: performing a first active voltage contrast test to the sample to show an open circuit point and making a first scratch mark at an adjacent position of the open circuit point; step 3: forming a coating mark at the first scratch mark on the sample; step 4: performing a second active voltage contrast test to the sample to show the open circuit point and locating a relative position of the open circuit point by using a position of the coating mark as a reference position.

Abstract: A redistribution layer with a landing pad is formed over a substrate with one or more mesh holes extending through the landing pad. The mesh holes may be arranged in a circular shape, and a passivation layer may be formed over the landing pad and the mesh holes. An opening is formed through the passivation layer and an underbump metallization is formed in contact with an exposed portion of the landing pad and extends over the mesh holes. By utilizing the mesh holes, sidewall delamination and peeling that might otherwise occur may be reduced or eliminated.

Abstract: A method includes planarizing a protective layer over gate materials overlying a recessed region in a substrate. The planarizing includes forming a first planarized surface by planarizing a sacrificial layer over the protective layer, and forming a second planarized surface of the protective layer by etching the first planarized surface of the sacrificial layer at an even rate across the recessed region. An etch mask layer is formed over the second planarized surface, and control gate stacks are formed in the recessed region by etching the gate materials.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a <100> crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a <110> crystalline direction along the first direction.

Abstract: A method includes forming a semiconductor fin over a substrate; forming first, second, and third gate structures crossing the semiconductor fin; forming first and second epitaxial source/drain structures on opposite sides of the first gate structure, and forming third and fourth source/drain epitaxial structures on opposite sides of the third gate structure; forming first gate spacers, second gate spacers, third gate spacers on opposite sidewalls of the first, second, and third gate structures, respectively; forming a first hard mask over the first, second, and third gate structures; patterning the first hard mask to form a first opening; etching a portion of the second gate structure and a portion of the semiconductor fin through the first opening to form a recess; and forming a dielectric layer in the recess, in which a dielectric constant of the dielectric layer is lower than a dielectric constant of silicon oxide.

Abstract: The present disclosure is directed to automated generation and management of update estimates relative to application of an update to a computing device. One or more updated to be applied to a computing device are identified. A trained artificial intelligence (AI) model is applied that is adapted to generate an update estimate predicting an amount of time that is required to apply an update to the computing device. An update estimate is generated based on a contextual analysis that evaluates one or more of: parameters associated with the update; device characteristics of the computing device to be updated; a state of current user activity on the computing device; historical predictions relating to prior update estimates for one or more computing devices (e.g., that comprise the computing device); or a combination thereof. A notification of the update estimate is then automatically generated and caused to be rendered.

Abstract: A wall of a building includes a wall body that is recessed to form multiple installation spaces, and a water supply unit that is disposed inside the wall body, and that includes multiple water pipes connected to the installation spaces and multiple actuated valves mounted to the water pipes. Each of the actuated valves, when opened, allows flow of water supplied via one of the water pipes to an installation space. The wall further includes a power supply circuit and multiple power units. Each of the power units includes a power storage module, a battery management system, and an emergency module. The battery management system controls a corresponding actuated valve to open when an operating value is higher than a predetermined value. The emergency module controls the corresponding actuated valve to open when the emergency module loses connection to the battery management system.

Abstract: A projection apparatus is provided, including a lens module, a movement element, a sensing element, and a lens control element. When the lens module moves to the origin position, the lens control element controls an image beam to focus on a first position on a reference plane in one of the tele mode and the wide mode, the lens control element controls the image beam to focus on a second position on the reference plane in the other mode, and the lens control element determines whether there is an offset between the first position and the second position. When the offset exists, the lens control element adjusts a movement parameter value of the movement element based on the offset value between the first position and the second position, so that the image beam is focused on the same position on the reference plane in the tele mode and wide mode.