Abstract: Some implementations described herein include systems and techniques for fabricating a wafer-on-wafer product using a filled lateral gap between beveled regions of wafers included in a stacked-wafer assembly and along a perimeter region of the stacked-wafer assembly. The systems and techniques include a deposition tool having an electrode with a protrusion that enhances an electromagnetic field along the perimeter region of the stacked-wafer assembly during a deposition operation performed by the deposition tool. Relative to an electromagnetic field generated by a deposition tool not including the electrode with the protrusion, the enhanced electromagnetic field improves the deposition operation so that a supporting fill material may be sufficiently deposited.

Abstract: A sealing article includes a body and a coating layer disposed on at least one surface of the body. The body comprises a polymeric elastomer such as perfluoroelastomer or fluoroelastomer. The coating layer comprises at least one metal. The sealing article may be a seal, a gasket, an O-ring, a T-ring or any other suitable product. The sealing article is resistant to ultra-violet (UV) light and plasma, and may be used for sealing a semiconductor processing chamber.

Abstract: A semiconductor device according to embodiments of the present disclosure includes a first die including a first bonding layer and a second die including a second hybrid bonding layer. The first bonding layer includes a first dielectric layer and a first metal coil embedded in the first dielectric layer. The second bonding layer includes a second dielectric layer and a second metal coil embedded in the second dielectric layer. The second hybrid bonding layer is bonded to the first hybrid bonding layer such that the first dielectric layer is bonded to the second dielectric layer and the first metal coil is bonded to the second metal coil.

Abstract: A capacitor structure and a manufacturing method thereof are disclosed in this invention. The capacitor structure includes a first electrode, a second electrode, and a capacitor dielectric stacked layer. The capacitor dielectric stacked layer is disposed between the first electrode and the second electrode, and the capacitor dielectric stacked layer includes a first dielectric layer. The first dielectric layer includes a first zirconium oxide layer and a first zirconium silicon oxide layer. A manufacturing method of a capacitor structure includes the following steps. A capacitor dielectric stacked layer is formed on a first electrode, and the capacitor dielectric stacked layer includes a first dielectric layer. The first dielectric layer includes a first zirconium oxide layer and a first zirconium silicon oxide layer. Subsequently, a second electrode is formed on the capacitor dielectric stacked layer, and the capacitor dielectric stacked layer is located between the first electrode and the second electrode.

Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure.

Abstract: A method includes planarizing a protective layer over gate materials overlying a recessed region in a substrate. The planarizing includes forming a first planarized surface by planarizing a sacrificial layer over the protective layer, and forming a second planarized surface of the protective layer by etching the first planarized surface of the sacrificial layer at an even rate across the recessed region. An etch mask layer is formed over the second planarized surface, and control gate stacks are formed in the recessed region by etching the gate materials.

Abstract: The present disclosure, in some embodiments, relates an integrated chip. The integrated chip includes a substrate. A through-substrate-via (TSV) extends through the substrate. A dielectric liner separates the TSV from the substrate. The dielectric liner is along one or more sidewalls of the substrate. The TSV includes a horizontally extending surface and a protrusion extending outward from the horizontally extending surface. The TSV has a maximum width along the horizontally extending surface.

Abstract: The present invention relates to the technical field of water surface waste treatment, and in particular to a water surface floater collecting ship. The technical problems are: picking up floaters with the cooperation of labors consumes manpower and causes disturbance of water surface, which makes the floaters float further away with water waves, and the odor emitted by the collected floating waste will pollute the environment and affect the salvage efficiency. The technical solution is: a water surface floater collecting ship, comprising a hull, a collecting system, etc.; the left part of the hull is connected with the collecting system used for collecting waste.

Abstract: Some implementations described herein provide an exposure tool. The exposure tool includes a reticle deformation detector and one or more processors configured to obtain, via the reticle deformation detector, reticle deformation information associated with a reticle during a scanning process for scanning multiple fields of a wafer. The one or more processors determine, based on the reticle deformation information, a deformation of the reticle at multiple times during the scanning process, and perform, based on the deformation of the reticle at the multiple times, one or more adjustments of one or more components of the exposure tool during the scanning process.

Abstract: Semiconductor processing apparatuses and methods are provided in which an electrostatic discharge (ESD) prevention layer is utilized to prevent or reduce ESD events from occurring between a semiconductor wafer and one or more components of the apparatuses. In some embodiments, a semiconductor processing apparatus includes a wafer handling structure that is configured to support a semiconductor wafer during processing of the semiconductor wafer. The apparatus further includes an ESD prevention layer on the wafer handling structure. The ESD prevention layer includes a first material and a second material, and the second material has an electrical conductivity that is greater than an electrical conductivity of the first material.

Abstract: Examples of an integrated circuit with gate cut features and a method for forming the integrated circuit are provided herein. In some examples, a workpiece is received that includes a substrate and a plurality of fins extending from the substrate. A first layer is formed on a side surface of each of the plurality of fins such that a trench bounded by the first layer extends between the plurality of fins. A cut feature is formed in the trench. A first gate structure is formed on a first fin of the plurality of fins, and a second gate structure is formed on a second fin of the plurality of fins such that the cut feature is disposed between the first gate structure and the second gate structure.

Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.

Abstract: A package structure includes a thermal dissipation structure, a first encapsulant, a die, a through integrated fan-out via (TIV), a second encapsulant, and a redistribution layer (RDL) structure. The thermal dissipation structure includes a substrate and a first conductive pad disposed over the substrate. The first encapsulant laterally encapsulates the thermal dissipation structure. The die is disposed on the thermal dissipation structure. The TIV lands on the first conductive pad of the thermal dissipation structure and is laterally aside the die. The second encapsulant laterally encapsulates the die and the TIV. The RDL structure is disposed on the die and the second encapsulant.

Abstract: Provided are a search result presentation method, a readable medium and a terminal device. The search result presentation method includes steps described below. In response to a search instruction for a target entity object, at least one multimedia resource for presenting the use effect of the target entity object is acquired, where the at least one multimedia resource is obtained based on multimedia content corresponding to the target entity object; and the at least one multimedia resource is presented.

Abstract: An optoelectronic computing system includes a first semiconductor die having a photonic integrated circuit (PIC) and a second semiconductor die having an electronic integrated circuit (EIC). The PIC includes optical waveguides, in which input values are encoded on respective optical signals carried by the optical waveguides. The PIC includes an optical copying distribution network having optical splitters. The PIC includes an array of optoelectronic circuitry sections, each receiving an optical wave from one of the output ports of the optical copying distribution network, and each optoelectronic circuitry section includes: at least one photodetector detecting at least one optical wave from the optoelectronic operation. The EIC includes electrical input ports receiving respective electrical values.

Abstract: An electronic device including a display device is provided. The display device includes a sharing area, a junction area, and a privacy area. The junction area is positioned between the sharing area and the privacy area. The display device includes a privacy panel. A transmittance of the privacy panel corresponding to the sharing area is greater than a transmittance of the privacy panel corresponding to the junction area, and the transmittance of the privacy panel corresponding to the junction area is greater than a transmittance of the privacy panel corresponding to the privacy area.

Abstract: In various examples, surface profile estimation and bump detection may be performed based on a three-dimensional (3D) point cloud. The 3D point cloud may be filtered in view of a portion of an environment including drivable free-space, and within a threshold height to factor out other objects or obstacles other than a driving surface and protuberances thereon. The 3D point cloud may be analyzed—e.g., using a sliding window of bounding shapes along a longitudinal or other heading direction—to determine one-dimensional (1D) signal profiles corresponding to heights along the driving surface. The profile itself may be used by a vehicle—e.g., an autonomous or semi-autonomous vehicle—to help in navigating the environment, and/or the profile may be used to detect bumps, humps, and/or other protuberances along the driving surface, in addition to a location, orientation, and geometry thereof.

Abstract: Systems and methods for simulating subterranean regions having multi-scale, complex fracture geometries in a realistic simulation environment, which includes in the modeling process three-dimensional multi-scale rock discontinuities, hydraulic fractures, and heterogenous reservoir properties. Non-intrusive embedded discrete fracture modeling formulations are applied in conjunction with commercial or in-house simulators to efficiently and accurately model subsurface characteristics including three-dimensional geometries having combinations of complex hydraulic fractures and multi-scale rock discontinuities.

Abstract: An implantable rotator cuff muscle suture spacer with pressure sensing is provided, formed by a semiconductor manufacture procedure, including a base layer, made of a polymer material and having flexibility, and further including a first configuration region and a second configuration region, where the base layer is folded at imaginary fold line positions of the first configuration region and the second configuration region, so that the first configuration region is located above the second configuration region; a first electrode region, deposited on the first configuration region; a second electrode region, deposited on the second configuration region, corresponding to a position below the first electrode region, and configured to obtain a pressure sensing value; an inductance coil, deposited on the second configuration region and surrounding the second electrode region; and a capacitor layer, coated above a surface of the base layer to form a dielectric substance.

Abstract: A method includes transferring a wafer to a position over a wafer chuck; lifting a lifting pin through the wafer chuck to a first position to support the wafer; holding the wafer on the lifting pin using a negative pressure source in gaseous communication with an inner gas passage of the lifting pin; introducing a gas to a region between the wafer and the wafer chuck through an outer gas passage of the lifting pin, wherein in a top view of the lifting pin, the inner gas passage has a circular profile, while the outer gas passage has a ring-shape profile; and lowering the lifting to dispose the wafer over the wafer chuck.