Patents by Inventor Cheng Chan

Cheng Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9837542
    Abstract: A polycrystalline silicon thin-film transistor includes a substrate; an isolation layer formed on the substrate; and a polycrystalline silicon active layer formed on the substrate and the isolation layer, with two source-drain ion implantation regions being formed at both sides of the active layer, wherein the edges at both ends of the isolation layer are within the edges at both ends of the active layer. In the polycrystalline silicon thin-film transistor and the method for manufacturing the same, it is possible to increase the grain size of the active layer, improve the grain uniformity in a channel region thereof, effectively prevent deterioration of characteristics of the active layer caused by backlight irradiation, and improve the reliability of the device.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: December 5, 2017
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zheng Liu, Chunping Long, Yu-Cheng Chan, Xiaoyong Lu, Xialong Li
  • Patent number: 9835636
    Abstract: Embodiments relate to serological markers for detecting the colorectal cancer and applications of the serological markers. A phospholipid scramblase1 (PLSCR1), a stomatin-like protein 2 (STOML2) or a transport protein Sec61? (SEC61?) increases expression in the blood at the earlier stage of the colorectal cancer. Detecting the expression of the PLSCR1, STOML2 or SEC61? protein or an induced autoantibody of each protein in a blood sample is used to diagnose the colorectal cancer. Moreover, the serological marker improves the detection efficiency and the sensitivity in detecting the colorectal cancer and is used to predict the prognosis. The serological markers are applied in preparing a detection device or inhibiting the growth of the colorectal cancer cells.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: December 5, 2017
    Assignee: CHANG GUNG UNIVERSITY
    Inventors: Err-Cheng Chan, Kuei-Tien Chen, Jau-Song Yu, Yu-Sun Chang, Jinn-Shiun Chen
  • Publication number: 20170338178
    Abstract: A method, for forming a semiconductor device structure, includes: forming a conductive structure over a substrate, wherein the conductive structure includes twin boundaries. The forming the conductive structure includes: manipulating process conditions so as to promote formation of the twin boundaries and yet control a density of the twin boundaries to be outside a range for which a portion of a curve is an asymptote of a constant value, the curve representing values of an atomic migration ratio corresponding to values of the density of the twin boundaries.
    Type: Application
    Filed: August 9, 2017
    Publication date: November 23, 2017
    Inventors: Jian-Hong LIN, Chwei-Ching CHIU, Yung-Huei LEE, Chien-Neng LIAO, Yu-Lun CHUEH, Tsung-Cheng CHAN, Chun-Lung HUANG
  • Publication number: 20170269409
    Abstract: Various embodiments provide a thin film transistor (TFT), a fabrication method thereof, and a display apparatus including the TFT. A carbon nanotube layer is formed over a substrate. The carbon nanotube layer includes a first plurality of carbon nanotubes. A plurality of gaps are formed through the carbon nanotube layer to provide a first patterned carbon nanotube layer. Carbon nanotube structures each including a second plurality of carbon nanotubes are formed in the plurality of gaps. The carbon nanotube structures have a carrier mobility different from the first patterned carbon nanotube layer, thereby forming an active layer for forming active structures of the thin-film transistor.
    Type: Application
    Filed: September 15, 2015
    Publication date: September 21, 2017
    Applicant: BOE Technology Group Co., Ltd.
    Inventors: SHUAI ZHANG, YU CHENG CHAN
  • Patent number: 9761523
    Abstract: A semiconductor device structure with twin-boundaries and method for forming the same are provided. The semiconductor device structure includes a substrate and a conductive structure formed over the substrate. The conductive structure includes twin boundaries, and a density of the twin boundaries is in a range from about 25 ?m?1 to about 250 ?m?1.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: September 12, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jian-Hong Lin, Chwei-Ching Chiu, Yung-Huei Lee, Chien-Neng Liao, Yu-Lun Chueh, Tsung-Cheng Chan, Chun-Lung Huang
  • Publication number: 20170207194
    Abstract: A chip package is provided. The chip package includes a first chip including a carrier substrate and a device substrate thereon. A second chip is mounted on the device substrate. A portion of the device substrate extends outward from the edge of the second chip, so as to be exposed from the second chip. A conductive pad is between the device substrate and the second chip. A polymer protective layer conformally covers the second chip, the exposed portion of the device substrate, and the edge of the carrier substrate. A redistribution layer is disposed on the polymer protective layer and extends into a first opening that passes through the polymer protective layer and the second chip and exposes the conductive pad, so as to be electrically connected to the conductive pad.
    Type: Application
    Filed: January 18, 2017
    Publication date: July 20, 2017
    Inventors: Hsing-Lung SHEN, Jiun-Yen LAI, Yu-Ting HUANG, Tsung-Cheng CHAN, Jan-Lian LIAO, Hung-Chang CHEN, Ming-Chieh HUANG, Hsi-Chien LIN
  • Publication number: 20170187763
    Abstract: The disclosure provides a streaming service system, a streaming service method and a controller thereof The streaming service system includes a plurality of switch nodes, a plurality of surrogate servers, a content management apparatus and a controller. The switch nodes are connected, and the surrogate servers are respectively connected to one of the switch nodes. The controller is connected to the switch nodes and communicates with the content management apparatus. The content management apparatus provides server information of the surrogate servers to the controller. When a first client apparatus is joined to a streaming group, the content management apparatus informs the controller. Further, the controller selects a first surrogate server from the surrogate servers, and sets at least a portion of the switch nodes to adjust a multicast tree. The first surrogate server transmits streaming packets to the first client through a first transmission route of the multicast tree.
    Type: Application
    Filed: December 30, 2015
    Publication date: June 29, 2017
    Inventors: Ming-Hung Hsu, Chien-Chao Tseng, Min-Cheng Chan, Hsing-Liang Ku, Ming-Hao Chou
  • Patent number: 9673333
    Abstract: A method for fabricating a Polysilicon Thin-Film Transistor is provided. The method includes forming a polysilicon active layer, forming a first gate insulation layer and a first gate electrode sequentially on the active layer, conducting a first ion implantation process on the active layer by using the first gate electrode as a mask to form two doped regions at ends of the active layer, forming a second gate insulation layer and a second gate electrode sequentially on the first gate insulation layer and the first gate electrode, and conducting a second ion implantation process on the active layer by using the second gate electrode as another mask to form two source/drain implantation regions at two outer sides of the doped regions of the active layer. Accordingly, impurity concentration of the two doped regions is smaller than that of the two source/drain implantation regions.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: June 6, 2017
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Zheng Liu, Xiaoyong Lu, Xiaolong Li, Yu-Cheng Chan
  • Publication number: 20170133512
    Abstract: The disclosure provides a polycrystalline silicon thin-film transistor and a method for manufacturing the same as well as a display device. The polycrystalline silicon thin-film transistor comprises: a substrate; an isolation layer formed on the substrate; and a polycrystalline silicon active layer formed on the substrate and the isolation layer, with two source-drain ion implantation regions being formed at both sides of the active layer, wherein the edges at both ends of the isolation layer are within the edges at both ends of the active layer. In the polycrystalline silicon thin-film transistor and the method for manufacturing the same provided by the disclosure, it is possible to increase the grain size of the active layer, improve the grain uniformity in a channel region thereof, effectively prevent deterioration of characteristics of the active layer caused by backlight irradiation, and improve the reliability of the device.
    Type: Application
    Filed: July 17, 2015
    Publication date: May 11, 2017
    Inventors: Zheng Liu, Chunping Long, Yu-Cheng Chan, Xiaoyong Lu, Xiaolong Li
  • Publication number: 20170053865
    Abstract: A semiconductor device structure with twin-boundaries and method for forming the same are provided. The semiconductor device structure includes a substrate and a conductive structure formed over the substrate. The conductive structure includes twin boundaries, and a density of the twin boundaries is in a range from about 25 ?m?1 to about 250 ?m?1.
    Type: Application
    Filed: August 21, 2015
    Publication date: February 23, 2017
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Jian-Hong LIN, Chwei-Ching CHIU, Yung-Huei LEE, Chien-Neng LIAO, Yu-Lun CHUEH, Tsung-Cheng CHAN, Chun-Lung HUANG
  • Publication number: 20170053954
    Abstract: Preparation methods for a thin-film layer pattern, thin-film transistor and array substrate. The preparation method for a thin-film layer pattern includes: providing a mask plate, the mask plate including a mask plate body and a hollowed portion arranged on same; placing the mask plate onto a substrate, and allowing a projection of the hollowed portion on the substrate to be overlapped with a projection of a thin-film layer pattern to be formed on the substrate; forming a thin film on the substrate on which the mask plate (10) is placed, wherein a first thin-film portion formed at the hollowed portion is disconnected from a second thin-film portion formed on the mask plate body; and stripping the mask plate, and reserving the first thin-film portion to form the thin-film layer pattern.
    Type: Application
    Filed: February 23, 2016
    Publication date: February 23, 2017
    Inventors: Chien Hung LIU, Yu Cheng CHAN
  • Publication number: 20170016889
    Abstract: A device is provided for detecting amplified products of nucleic acid, the device can detect at least one analyte molecule comprising a first marker and a second marker. This device sequentially comprises the following sections along an axial direction: a sample contact section where the analyte molecule is absorbed, a combining section where the analyte molecule is received comprises a reporting carrier specifically bound with the first marker, and a detecting section comprises at least one color reaction section comprising a control unit point having a first combining molecule for specifically binding with the reporting carrier and presenting color, and at least one testing unit point having a second combining molecule for specifically binding with the second marker and presenting color. The control unit point and the testing unit point are separated from each other, and a line connecting them is not parallel to the axial direction.
    Type: Application
    Filed: December 17, 2015
    Publication date: January 19, 2017
    Inventor: ERR-CHENG CHAN
  • Publication number: 20170018652
    Abstract: A method for fabricating a Polysilicon Thin-Film Transistor is provided. The method includes forming a polysilicon active layer, forming a first gate insulation layer and a first gate electrode sequentially on the active layer, conducting a first ion implantation process on the active layer by using the first gate electrode as a mask to form two doped regions at ends of the active layer, forming a second gate insulation layer and a second gate electrode sequentially on the first gate insulation layer and the first gate electrode, and conducting a second ion implantation process on the active layer by using the second gate electrode as another mask to form two source/drain implantation regions at two outer sides of the doped regions of the active layer. Accordingly, impurity concentration of the two doped regions is smaller than that of the two source/drain implantation regions.
    Type: Application
    Filed: February 22, 2016
    Publication date: January 19, 2017
    Applicant: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zheng LIU, Xiaoyong LU, Xiaolong LI, Yu-Cheng CHAN
  • Publication number: 20170013514
    Abstract: The present invention provides a system and a method for service continuity in heterogeneous wireless networks, which comprises a handover decision module and a session continuity module. The handover decision module is responsible for maintaining link layer association and network layer reachability in according to the underlying network conditions to fulfill the service requirement of applications. When acting as a sender, the session continuity module will select transmission path(s), reestablish the transport connection(s) and tag packets with session IDs and sequence numbers. When acting as a receiver, the session continuity module will identify and reorder packets using session IDs and sequence numbers, regardless of the IP addresses and ports of the packets. To sum up, the present invention can provide service continuity and multipath transmission for network devices.
    Type: Application
    Filed: September 26, 2016
    Publication date: January 12, 2017
    Inventors: CHIEN-CHAO TSENG, MIN-CHENG CHAN
  • Publication number: 20170005115
    Abstract: The present disclosure provides a method for forming an active layer with a pattern. The method includes forming an amorphous silicon layer and forming a function layer on the amorphous silicon layer. The function layer has a same pattern as the active layer. The method further includes performing a crystallization process for converting the amorphous silicon layer to a poly-silicon layer. The poly-silicon layer has first portions covered by the function layer and second portions not covered by the function layer, and grain sizes of the poly-silicon in the first portions are larger than grain sizes of the poly-silicon in the second portions.
    Type: Application
    Filed: August 14, 2015
    Publication date: January 5, 2017
    Inventors: ZUQIANG WANG, CHIEN HUNG LIU, YU CHENG CHAN, LUJIANG HUANGFU
  • Publication number: 20160359359
    Abstract: A power supply apparatus includes a bulk capacitor, a voltage dropper unit and a pre-charging capacitor. The voltage dropper unit is electrically connected to the bulk capacitor. The pre-charging capacitor is electrically connected to the voltage dropper unit. When the power supply apparatus receives an input direct current voltage, a voltage of the bulk capacitor is provided with a first voltage, and the pre-charging capacitor is charged so that the pre-charging capacitor is provided with a second voltage, and the second voltage is greater than the first voltage. When the voltage of the bulk capacitor is less than a predetermined voltage, the second voltage of the pre-charging capacitor is converted voltage by the voltage dropper unit to provide for extending a hold up time of the power supply apparatus.
    Type: Application
    Filed: February 2, 2016
    Publication date: December 8, 2016
    Inventors: Cheng-Chan HSU, Yi-Sheng CHANG
  • Publication number: 20160201138
    Abstract: The disclosure discloses a method and markers for assessing the risk of having colorectal cancer for an individual by a stool sample. The method includes: detecting expression levels of a first microRNA and a second microRNA in the stool sample; and assessing the risk of having colorectal cancer for the individual based on a ratio between the expression levels of the first microRNA and the second microRNA. Here, the first microRNA is miR-223, miR-25, or miR-93, and the second microRNA is miR-221, miR-222, miR-21, miR-93, miR-141, miR-200c, miR-191, miR-17, miR-148a, miR-106a, miR-195, miR-20a, miR-181b, miR-145, miR-155, miR-106b, miR-24, miR-19b, miR-130b, or miR-18a. When the first microRNA is miR-93, the second microRNA is miR-17, miR-106a, miR-195, miR-20a, miR-181b, miR-155, miR-24, miR-19b, or miR-18a.
    Type: Application
    Filed: October 30, 2015
    Publication date: July 14, 2016
    Inventors: Jinn- Shiun CHEN, Yu-Sun CHANG, Err-Cheng CHAN, Chia-Chun CHEN, Pi-Yueh CHANG
  • Publication number: 20160201139
    Abstract: The disclosure discloses a method and markers for assessing the risk of having colorectal cancer by a blood sample obtained from an individual. The assessment method includes the steps of: detecting expression levels of a first microRNA and a second microRNA in the blood sample; and assessing the risk of having colorectal cancer for the individual based on a ratio between the expression levels of the first microRNA and the second microRNA. Here, the first microRNA is miR-221, miR-92a, miR-15a, miR-24, miR-18a, miR-191, miR-128, or miR-223, and the second microRNA is miR-10b, miR-100, miR-29a, miR-126, miR-139, miR-31, miR-145, or miR-155. When the first microRNA is miR-128, the second microRNA is miR-10b, miR-100, miR-29a, miR-126, miR-139, miR-31, or miR-145.
    Type: Application
    Filed: October 30, 2015
    Publication date: July 14, 2016
    Inventors: Jinn- Shiun CHEN, Yu-Sun CHANG, Err-Cheng CHAN, Chia-Chun CHEN, Pi-Yueh CHANG
  • Patent number: 9362748
    Abstract: A power system with a combination of active current sharing and droop current sharing is disclosed. The power system includes a system load and plural power supplies connected with each other and connected to the system load. The power supplies are configured to respectively output a load current to the system load, and each power supply includes an active current sharing circuit and a droop current sharing circuit. The active current sharing circuit is configured to enter an operation or shutdown mode depending on whether the load current is higher than a first current set point. The droop current sharing circuit is configured to enter an operation or shutdown mode depending on whether the load current is higher than a second current set point. Hence, each power supply can respectively output an equal share of the load current by an active current sharing technique and/or a droop current sharing technique.
    Type: Grant
    Filed: January 2, 2013
    Date of Patent: June 7, 2016
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Cheng-Chan Hsu, Chan-Chia Yeh, Chien-An Lai
  • Patent number: 9251742
    Abstract: An electrophoretic display apparatus and an image-updating method thereof are provided. The electrophoretic display apparatus comprises a display panel and a source driver. The display panel comprises a plurality of pixels and a plurality of source lines, and each pixel electrode is electrically coupled to an AC common voltage through a corresponding capacitor. The capacitor comprises a plurality of charged particles. The source driver comprises a first data-latching circuit and a second data-latching circuit. Each of the data-latching circuits comprises a transistor, a capacitor and an inverter. The first data-latching circuit receives image data and a data shift-register output pulse. The second data-latching circuit is electrically coupled between an output terminal of the first data-latching circuit and a source line and is used for receiving a data output pulse.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: February 2, 2016
    Assignee: AU OPTRONICS CORP.
    Inventors: Ping-Sheng Kuo, Hsiang-Lin Lin, Chih-Cheng Chan, Sheng-Wen Huang