Patents by Inventor Cheng-Chi Chuang
Cheng-Chi Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240021707Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a gate structure sandwiched between and in contact with a first spacer feature and a second spacer feature, a top surface of the first spacer feature and a top surface of the second spacer feature extending above a top surface of the gate structure, a gate self-aligned contact (SAC) dielectric feature over the first spacer feature and the second spacer feature, a contact etch stop layer (CESL) over the gate SAC dielectric feature, a dielectric layer over the CESL, a gate contact feature extending through the dielectric layer, the CESL, the gate SAC dielectric feature, and between the first spacer feature and the second spacer feature to be in contact with the gate structure, and a liner disposed between the first spacer feature and the gate contact feature.Type: ApplicationFiled: August 3, 2023Publication date: January 18, 2024Inventors: Li-Zhen Yu, Lin-Yu Huang, Chia-Hao Chang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
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Publication number: 20240021616Abstract: A semiconductor structure includes an isolation structure, a source/drain region over the isolation structure, a gate structure over the isolation structure and adjacent to the source/drain region, an interconnect layer over the source/drain region and the gate structure, an isolating layer below the gate structure, and a contact structure under the source/drain region. The contact structure has a first portion and a second portion. The first portion is below the second portion. The second portion extends through the isolating layer and protrudes above the isolating layer. A portion of the isolating layer is vertically between the gate structure and the first portion of the contact structure.Type: ApplicationFiled: July 21, 2023Publication date: January 18, 2024Inventors: Chun-Yuan Chen, Huan-Chieh Su, Cheng-Chi Chuang, Chih-Hao Wang
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Publication number: 20240021682Abstract: A method includes forming a dummy gate structure over a substrate; forming a source/drain structure over the substrate; replacing the dummy gate structure with a metal gate structure; forming a protection cap over the metal gate structure; forming a source/drain contact over the source/drain structure; performing a selective deposition process to form a first etch stop layer on the protection cap, in which the selective deposition process has a faster deposition rate on the protection cap than on the source/drain contact; depositing a second etch stop layer over the first etch stop layer the source/drain contact; etching the second etch stop layer to form an opening; and forming a via contact in the opening.Type: ApplicationFiled: July 14, 2023Publication date: January 18, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Li-Zhen YU, Chia-Hao CHANG, Cheng-Chi CHUANG, Yu-Ming LIN, Chih-Hao WANG
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Publication number: 20240021711Abstract: A semiconductor structure is provided, and includes a first fin structure, a second fin structure, and a third fin structure over a substrate. The second fin structure is located between the first fin structure and the third fin structure. The semiconductor structure also includes a fin isolation structure formed between the first fin structure and the third fin structure; and a gate structure formed over the first fin structure, the second fin structure, the third fin structure and the fin isolation structure. The semiconductor structure further includes a plurality of epitaxial structures formed over the first fin structure, the second fin structure and the third fin structure. The semiconductor structure includes a dielectric material over the first epitaxial structure, the second epitaxial structure, and the third epitaxial structure; and a contact formed in the dielectric material and connected to the first epitaxial structure and the third epitaxial structure.Type: ApplicationFiled: July 14, 2022Publication date: January 18, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yun-Ju FAN, Lin-Yu HUANG, Sheng-Tsung WANG, Huan-Chieh SU, Cheng-Chi CHUANG, Chih-Hao WANG
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Patent number: 11862561Abstract: In an embodiment, a method of forming a structure includes forming a first transistor and a second transistor over a first substrate; forming a front-side interconnect structure over the first transistor and the second transistor; etching at least a backside of the first substrate to expose the first transistor and the second transistor; forming a first backside via electrically connected to the first transistor; forming a second backside via electrically connected to the second transistor; depositing a dielectric layer over the first backside via and the second backside via; forming a first conductive line in the dielectric layer, the first conductive line being a power rail electrically connected to the first transistor through the first backside via; and forming a second conductive line in the dielectric layer, the second conductive line being a signal line electrically connected to the second transistor through the second backside via.Type: GrantFiled: December 18, 2020Date of Patent: January 2, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shang-Wen Chang, Yi-Hsun Chiu, Cheng-Chi Chuang, Ching-Wei Tsai, Wei-Cheng Lin, Shih-Wei Peng, Jiann-Tyng Tzeng
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Patent number: 11862559Abstract: A semiconductor structure includes a semiconductor substrate, a metallization feature over the semiconductor substrate, a first dielectric feature, a second dielectric feature, and a via contact. The metallization feature includes a first bottom corner and a second bottom corner opposite to the first bottom corner. The first dielectric feature is adjacent to the first bottom corner, and the second dielectric feature is adjacent to the second bottom corner. The metallization feature is interposed between the first dielectric feature and the second dielectric feature. In some embodiments, an included angle of the first bottom corner defined by a sidewall of first dielectric feature and a bottom surface of the metallization feature is less than 90°. The via contact is configured to connect the metallization feature to the semiconductor substrate.Type: GrantFiled: June 3, 2021Date of Patent: January 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Lin-Yu Huang, Li-Zhen Yu, Cheng-Chi Chuang, Kuan-Lun Cheng, Chih-Hao Wang
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Patent number: 11854866Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip. The method includes forming a gate electrode over a substrate. The gate electrode is laterally separated from a dielectric by a spacer structure. A sacrificial layer is formed over a top surface of the gate electrode. A liner layer is formed along a sidewall of the spacer structure and on the sacrificial layer. The sacrificial layer is removed and a hard mask material is formed over the gate electrode. A part of the dielectric is removed to form a contact opening laterally separated from the gate electrode by the spacer structure. A conductive contact is formed within the contact opening.Type: GrantFiled: June 17, 2022Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Zhen Yu, Cheng-Chi Chuang, Chih-Hao Wang, Yu-Ming Lin, Lin-Yu Huang
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Publication number: 20230411485Abstract: An IC structure includes a first transistor, first gate spacers, a second transistor, second gate spacers, a backside metal line, and a metal contact. The first transistor includes first source/drain regions and a first gate structure between the first source/drain regions. The first gate spacers space apart the first source/drain regions from the first gate structure. The second transistor comprises second source/drain regions and a second gate structure between the second source/drain regions. The second gate spacers space apart the second source/drain regions from the second gate structure. The first gate spacers and the second gate spacers extend along a first direction. The backside metal line extends between the first transistor and the second transistor along a second direction. The first metal contact wraps around one of the second source/drain regions and has a protrusion interfacing the backside metal line.Type: ApplicationFiled: July 28, 2023Publication date: December 21, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Huan-Chieh SU, Li-Zhen YU, Chun-Yuan CHEN, Cheng-Chi CHUANG, Shang-Wen CHANG, Yi-Hsun CHIU, Pei-Yu WANG, Ching-Wei TSAI, Chih-Hao WANG
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Patent number: 11848372Abstract: A method provides a structure having a fin oriented lengthwise and widthwise along first and second directions respectively, an isolation structure adjacent to sidewalls of the fin, and first and second source/drain (S/D) features over the fin. The method includes forming an etch mask exposing a first portion of the fin under the first S/D feature and covering a second portion of the fin under the second S/D feature; removing the first portion of the fin, resulting in a first trench; forming a first dielectric feature in the first trench; and removing the second portion of the fin to form a second trench. The first dielectric feature and the isolation structure form first and second sidewalls of the second trench respectively. The method includes laterally etching the second sidewalls, thereby expanding the second trench along the second direction and forming a via structure in the expanded second trench.Type: GrantFiled: April 21, 2021Date of Patent: December 19, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Huan-Chieh Su, Li-Zhen Yu, Chun-Yuan Chen, Cheng-Chi Chuang, Kuan-Lun Cheng, Chih-Hao Wang
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Patent number: 11842967Abstract: The present disclosure describes a semiconductor structure having a power distribution network including first and second conductive lines. A substrate includes a first surface that is in contact with the power distribution network. A plurality of backside vias are in the substrate and electrically coupled to the first conductive line. A via rail is on a second surface of the substrate that opposes the first surface. A first interlayer dielectric is on the via rail and on the substrate. A second interlayer dielectric is on the first interlayer dielectric. A third interlayer dielectric is on the second interlayer dielectric. First and top interconnect layers are in the second and third interlayer dielectrics, respectively. Deep vias are in the interlayer dielectric and electrically coupled to the via rail. The deep vias are also connected to the first and top interconnect layers. A power supply in/out layer is on the third interlayer dielectric and in contact with the top interconnect layer.Type: GrantFiled: October 25, 2021Date of Patent: December 12, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kam-Tou Sio, Cheng-Chi Chuang, Chia-Tien Wu, Jiann-Tyng Tzeng, Shih-Wei Peng, Wei-Cheng Lin
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Patent number: 11842962Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first interconnect arranged within an inter-level dielectric (ILD) layer. The first interconnect has opposing sidewalls that are both laterally separated from closest neighboring interconnects within the ILD layer by one or more air-gaps along a cross-sectional view. A second interconnect is arranged within the ILD layer. The ILD layer laterally contacts opposing sidewalls of the second interconnect as viewed along the cross-sectional view.Type: GrantFiled: July 27, 2022Date of Patent: December 12, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tai-I Yang, Cheng-Chi Chuang, Yung-Chih Wang, Tien-Lu Lin
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Publication number: 20230387225Abstract: A semiconductor structure includes an epitaxial region having a front side and a backside. The semiconductor structure includes an amorphous layer formed over the backside of the epitaxial region, wherein the amorphous layer includes silicon. The semiconductor structure includes a first silicide layer formed over the amorphous layer. The semiconductor structure includes a first metal contact formed over the first silicide layer.Type: ApplicationFiled: August 9, 2023Publication date: November 30, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Chuan Chiu, Huan-Chieh Su, Pei-Yu Wang, Cheng-Chi Chuang, Chun-Yuan Chen, Li-Zhen Yu, Chia-Hao Chang, Yu-Ming Lin, Chih-Hao Wang
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Publication number: 20230387266Abstract: A semiconductor structure includes a power rail; an isolation structure over the power rail; first and second source/drain (S/D) features over the isolation structure, defining a first direction from the first S/D feature to the second S/D feature; one or more channel layers over the isolation structure and connecting the first and the second S/D features; a first via structure extending through the isolation structure and electrically connecting the first S/D feature and the power rail; and a first dielectric feature extending through the isolation structure and physically contacting the second S/D feature and the power rail. The first via structure has a first width in a first cross-section perpendicular to the first direction, the first dielectric feature has a second width in a second cross-section parallel to the first cross-section, and the first width is greater than the second width.Type: ApplicationFiled: August 7, 2023Publication date: November 30, 2023Inventors: Huan-Chieh Su, Li-Zhen Yu, Chun-Yuan Chen, Cheng-Chi Chuang, Kuan-Lun Cheng, Chih-Hao Wang
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Publication number: 20230387010Abstract: A method having a semiconductor substrate received and a first dielectric layer is formed over the semiconductor substrate. A trench is formed in the first dielectric layer. The trench is filled to form a conductive layer in the first dielectric layer. The conductive layer is segmented to form a first conductive feature and a second conductive feature separated from each other by a recess. The recess is filled with a second dielectric layer, such that one or both of the conductive features are end-capped by a portion of the first dielectric layer and a portion of the second dielectric layer.Type: ApplicationFiled: August 8, 2023Publication date: November 30, 2023Inventors: Lin-Yu Huang, Li-Zhen Yu, Cheng-Chi Chuang, Kuan-Lun Cheng, Chih-Hao Wang
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Publication number: 20230387220Abstract: A method includes providing a structure having source/drain electrodes and a first dielectric layer over the source/drain electrodes; forming a first etch mask covering a first area of the first dielectric layer; performing a first etching process to the first dielectric layer, resulting in first trenches over the source/drain electrodes; filling the first trenches with a second dielectric layer that has a different material than the first dielectric layer; removing the first etch mask; performing a second etching process including isotropic etching to the first area of the first dielectric layer, resulting in a second trench above a first one of the source/drain electrodes; depositing a metal layer into at least the second trench; and performing a chemical mechanical planarization (CMP) process to the metal layer.Type: ApplicationFiled: July 28, 2023Publication date: November 30, 2023Inventors: Meng-Huan Jao, Lin-Yu Huang, Sheng-Tsung Wang, Huan-Chieh Su, Cheng-Chi Chuang, Chih-Hao Wang
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Publication number: 20230386916Abstract: Semiconductor structures and methods of forming the same are provided. In one embodiment, a semiconductor structure includes an active region over a substrate, a gate structure disposed over the active region, and a gate contact that includes a lower portion disposed over the gate structure and an upper portion disposed over the lower portion.Type: ApplicationFiled: August 8, 2023Publication date: November 30, 2023Inventors: Cheng-Chi Chuang, Huan-Chieh Su, Sheng-Tsung Wang, Lin-Yu Huang, Chih-Hao Wang
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Publication number: 20230387115Abstract: A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.Type: ApplicationFiled: July 28, 2023Publication date: November 30, 2023Inventors: Huan-Chieh Su, Li-Zhen Yu, Chun-Yuan Chen, Shih-Chuan Chiu, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
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Publication number: 20230387035Abstract: The present disclosure describes a semiconductor structure having a power distribution network including first and second conductive lines. A substrate includes a first surface that is in contact with the power distribution network. A plurality of backside vias are in the substrate and electrically coupled to the first conductive line. A via rail is on a second surface of the substrate that opposes the first surface. A first interlayer dielectric is on the via rail and on the substrate. A second interlayer dielectric is on the first interlayer dielectric. A third interlayer dielectric is on the second interlayer dielectric. First and top interconnect layers are in the second and third interlayer dielectrics, respectively. Deep vias are in the interlayer dielectric and electrically coupled to the via rail. The deep vias are also connected to the first and top interconnect layers. A power supply in/out layer is on the third interlayer dielectric and in contact with the top interconnect layer.Type: ApplicationFiled: August 10, 2023Publication date: November 30, 2023Inventors: Kam-Tou SIO, Cheng-Chi Chuang, Chia-Tien Wu, Jiann-Tyng Tzeng, Shih-Wei Peng, Wei-Cheng Lin
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Publication number: 20230386905Abstract: A semiconductor structure includes first and second epitaxial features, at least one semiconductor channel layer connecting the first and second epitaxial features, and a gate structure engaging the semiconductor channel layer. The first and second epitaxial features, the semiconductor channel layer, and the gate structure are at a frontside of the semiconductor structure. The semiconductor structure also includes a backside metal wiring layer at a backside of the semiconductor structure, and a backside conductive contact electrically connecting the first epitaxial feature to the backside metal wiring layer. The backside metal wiring layer is spaced away from the gate structure with an air gap therebetween.Type: ApplicationFiled: August 8, 2023Publication date: November 30, 2023Inventors: Chia-Hao Chang, Lin-Yu Huang, Li-Zhen Yu, Cheng-Chi Chuang, Kuan-Lun Cheng, Chih-Hao Wang
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Patent number: 11830769Abstract: A semiconductor structure includes first and second source/drain (S/D) features, one or more semiconductor channel layers connecting the first and second S/D features, a gate structure engaging the one or more semiconductor channel layers, a metal wiring layer at a backside of the semiconductor structure, an S/D contact electrically connecting the first S/D feature to the metal wiring layer, and a seal layer between the metal wiring layer and the gate structure. The seal layer is spaced away from the gate structure by an air gap therebetween.Type: GrantFiled: July 20, 2022Date of Patent: November 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Hao Chang, Lin-Yu Huang, Li-Zhen Yu, Cheng-Chi Chuang, Kuan-Lun Cheng, Chih-Hao Wang