Patents by Inventor Cheng-Chi Chuang

Cheng-Chi Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Source/Drain Contacts and Methods of Forming Same
    Publication number: 20230120499
    Abstract: A device includes a device layer comprising a first transistor and a second transistor; a first interconnect structure on a front-side of the device layer; and a second interconnect structure on a backside of the device layer. The second interconnect structure comprising a first dielectric layer on the backside of the device layer, wherein a semiconductor material is disposed between the first dielectric layer and a first source/drain region of the first transistor; a contact extending through the first dielectric layer to a second source/drain region of the second transistor; and a first conductive line electrically connected to the second source/drain region of the second transistor through the contact.
    Type: Application
    Filed: December 19, 2022
    Publication date: April 20, 2023
    Inventors: Li-Zhen Yu, Huan-Chieh Su, Lin-Yu Huang, Cheng-Chi Chuang, Chih-Hao Wang
  • INTEGRATED CIRCUIT STRUCTURE WITH BACKSIDE INTERCONNECTION STRUCTURE HAVING AIR GAP
    Publication number: 20230121408
    Abstract: A method includes forming a transistor over a substrate; forming a front-side interconnection structure over the transistor; after forming the front-side interconnection structure, removing the substrate; after removing the substrate, forming a backside via to be electrically connected to the transistor; depositing a dielectric layer to cover the backside via; forming an opening in the dielectric layer to expose the backside via; forming a spacer structure on a sidewall of the opening; after forming a spacer structure, forming a conductive feature in the opening to be electrically connected to the backside via; and after forming the conductive feature, forming an air gap in the spacer structure.
    Type: Application
    Filed: December 14, 2022
    Publication date: April 20, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Zhen Yu, Huan-Chieh Su, Lin-Yu Huang, Cheng-Chi Chuang, Chih-Hao Wang
  • Semiconductor structure having an anchor-shaped backside via
    Patent number: 11631638
    Abstract: A semiconductor structure includes first and second source/drain (S/D) features, one or more channel layers connecting the first and the second S/D features, a high-k metal gate engaging the one or more channel layers, an isolation structure, a power rail under the isolation structure, and a via structure extending through the isolation structure and electrically connecting the first S/D feature and the power rail. At least a portion of the isolation structure is under the first and the second S/D features. In a cross-section that extends through the first S/D feature and perpendicular to a direction from the first S/D feature to the second S/D feature along the one or more channel layers, the via structure extends into a gap vertically between the first S/D feature and the isolation structure.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: April 18, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Yuan Chen, Huan-Chieh Su, Cheng-Chi Chuang, Chih-Hao Wang
  • METHOD FOR FORMING LONG CHANNEL BACK-SIDE POWER RAIL DEVICE
    Publication number: 20230106478
    Abstract: A method of forming a semiconductor transistor device. The method comprises forming a channel structure over a substrate and forming a first source/drain structure and a second source/drain structure on opposite sides of the fin structure. The method further comprises forming a gate structure surrounding the fin structure. The method further comprises flipping and partially removing the substrate to form a back-side capping trench while leaving a lower portion of the substrate along upper sidewalls of the first source/drain structure and the second source/drain structure as a protective spacer. The method further comprises forming a back-side dielectric cap in the back-side capping trench.
    Type: Application
    Filed: December 12, 2022
    Publication date: April 6, 2023
    Inventors: Huan-Chieh Su, Cheng-Chi Chuang, Chih-Hao Wang, Zhi-Chang Lin, Li-Zhen Yu
  • Semiconductor device with gate cut feature and method for forming the same
    Patent number: 11621197
    Abstract: Semiconductor devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece that has a substrate, a first plurality of channel members, a second plurality of channel members, a first gate structure engaging the first plurality of channel members, a second gate structure engaging the second plurality of channel members, a hybrid fin disposed between the first and second gate structures, and an isolation feature disposed under the hybrid fin. The method also includes forming a metal cap layer at a frontside of the workpiece. The metal cap layer electrically connects the first and second gate structures. The method also includes etching the isolation feature, etching the hybrid fin, etching the metal cap layer, and depositing a dielectric material to form a gate isolation feature disposed between the first and second gate structures.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: April 4, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Huan-Chieh Su, Li-Zhen Yu, Chun-Yuan Chen, Lo-Heng Chang, Cheng-Chi Chuang, Kuan-Lun Cheng, Chih-Hao Wang
  • Contact features and methods of fabricating the same in semiconductor devices
    Patent number: 11621224
    Abstract: A semiconductor structure includes a metal gate structure (MG) disposed over a semiconductor substrate, gate spacers disposed on sidewalls of the MG, and a gate contact disposed on the MG. The semiconductor structure further includes an etch-stop layer (ESL) disposed on the gate spacers, and a source/drain (S/D) contact disposed adjacent to the gate spacers, where a top portion of the S/D contact defined by the ESL is narrower than a bottom portion of the S/D contact defined by the gate spacers.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: April 4, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.
    Inventors: Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20230088037
    Abstract: A semiconductor structure includes a first conductive member, a second conductive member and a third conductive member. The first conductive member is extended through and is laterally surrounded by a first dielectric layer. The second conductive member is disposed over the first dielectric layer and the first conductive member, and is laterally surrounded by a second dielectric layer. The third conductive member is disposed over the second conductive member, and is laterally surrounded by the second dielectric layer, wherein a portion of the second conductive member is protruded into the third conductive member.
    Type: Application
    Filed: November 29, 2022
    Publication date: March 23, 2023
    Inventors: POKUAN HO, CHIA-TIEN WU, CHENG-CHI CHUANG
  • SEMICONDUCTOR DEVICE WITH BACKSIDE POWER RAIL AND METHODS OF FABRICATION THEREOF
    Publication number: 20230075343
    Abstract: A semiconductor device structure includes a source/drain feature comprising a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface. The structure also includes a dielectric layer having a continuous surface in contact with the entire second surface of the source/drain feature, a semiconductor layer having a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface, wherein the sidewall of the semiconductor layer is in contact with the sidewall of the source/drain feature. The structure also includes a gate dielectric layer in contact with the continuous surface of the dielectric layer and the second surface of the semiconductor layer, and a gate electrode layer surrounding a portion of the semiconductor layer.
    Type: Application
    Filed: November 14, 2022
    Publication date: March 9, 2023
    Inventors: Li-Zhen YU, Huan-Chieh SU, Shih-Chuan CHIU, Lin-Yu HUANG, Cheng-Chi CHUANG, Chih-Hao WANG
  • SEMICONDUCTOR DEVICE HAVING AIR GAP AND METHOD OF FABRICATING THEREOF
    Publication number: 20230067799
    Abstract: Methods and devices that provide for a fin structure and a dielectric fin structure. A gate structure is formed over the fin structure and the hybrid fin structure. A plurality of dielectric layers is adjacent the gate structure and over the hybrid fin structure between the gate structure and a contact element over the dielectric fin structure. The plurality of dielectric layers includes an air gap, formed by removal of a dummy spacer layer.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: Chia-Hao CHANG, Lin-Yu HUANG, Sheng-Tsung WANG, Cheng-Chi CHUANG, Kuan-Lun CHENG, Chih-Hao WANG
  • SEMICONDUCTOR DEVICES INCLUDING LOW-K METAL GATE ISOLATION AND METHODS OF FABRICATION THEREOF
    Publication number: 20230066705
    Abstract: Embodiments of the present disclosure provide semiconductor devices having conductive features with reduced height and increased width, and methods for forming the semiconductor devices. Particularly, sacrificial self-aligned contact (SAC) layer and sacrificial metal contact etch stop layer (M-CESL) are used to form conductive features with reduced resistance. After formation of the conductive features, the sacrificial SAC and sacrificial M-CESL are removed and replaced with a low-k material to reduce capacitance in the device. As a result, performance of the device is improved.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: Sheng-Tsung WANG, Chia-Hao CHANG, Lin-Yu HUANG, Cheng-Chi CHUANG, Chih-Hao WANG
  • Butted contacts and methods of fabricating the same in semiconductor devices
    Patent number: 11594602
    Abstract: A semiconductor structure includes a metal gate structure (MG) formed over a substrate, a first gate spacer formed on a first sidewall of the MG, a second gate spacer formed on a second sidewall of the MG opposite to the first sidewall, where the second gate spacer is shorter than the first gate spacer, a source/drain (S/D) contact (MD) adjacent to the MG, where a sidewall of the MD is defined by the second gate spacer, and a contact feature configured to electrically connect the MG to the MD.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: February 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Zhen Yu, Lin-Yu Huang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • FIELD EFFECT TRANSISTOR WITH MULTI-METAL GATE VIA AND METHOD
    Publication number: 20230053595
    Abstract: A device includes a substrate, a gate structure wrapping around a vertical stack of nanostructure semiconductor channels, and a source/drain abutting the vertical stack and in contact with the nanostructure semiconductor channels. The device includes a gate via in contact with the first gate structure. The gate via includes a metal liner layer having a first flowability, and a metal fill layer having a second flowability higher than the first flowability.
    Type: Application
    Filed: August 19, 2021
    Publication date: February 23, 2023
    Inventors: Sheng-Tsung WANG, Lin-Yu HUANG, Cheng-Chi CHUANG, Sung-Li WANG, Chih-Hao WANG
  • SEMICONDUCTOR STRUCTURE WITH ISOLATION FEATURE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20230047194
    Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and first nanostructures and second nanostructures formed over the substrate. The semiconductor structure also includes a gate structure including a first portion wrapping around the first nanostructures and a second portion wrapping around the second nanostructures. The semiconductor structure also includes a dielectric feature sandwiched between the first portion and the second portion of the gate structure. In addition, the dielectric feature includes a bottom portion and a top portion over the bottom portion, and the top portion of the dielectric feature includes a shell layer and a core portion surrounded by the shell layer.
    Type: Application
    Filed: March 16, 2022
    Publication date: February 16, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Yuan CHEN, Huan-Chieh SU, Li-Zhen YU, Lo-Heng CHANG, Cheng-Chi CHUANG, Chih-Hao WANG
  • Metal Contact Isolation and Methods of Forming the Same
    Publication number: 20230050249
    Abstract: A semiconductor device includes a first gate structure and a second gate structure over a fin, a dielectric cut pattern sandwiched by the first and second gate structures, and a liner layer surrounding the dielectric cut pattern. The dielectric cut pattern is spaced apart from the fin and extends further from the substrate than a first gate electrode of the first gate structure and a second gate electrode of the second gate structure. The semiconductor device further includes a conductive feature sandwiched by the first and second gate structures. The conductive feature is divided by the conductive feature into a first segment and a second segment. The first segment of the conductive feature is above a source/drain region of the fin.
    Type: Application
    Filed: April 26, 2022
    Publication date: February 16, 2023
    Inventors: Lin-Yu HUANG, Li-Zhen Yu, Huan-Chieh Su, Cheng-Chi Chuang, Chih-Hao Wang
  • Method for forming long channel back-side power rail device
    Patent number: 11581224
    Abstract: A method of forming a semiconductor transistor device. The method comprises forming a fin-shaped channel structure over a substrate and forming a first source/drain epitaxial structure and a second source/drain epitaxial structure on opposite endings of the fin structure. The method further comprises forming a metal gate structure surrounding the fin structure. The method further comprises flipping and partially removing the substrate to form a back-side capping trench while leaving a lower portion of the substrate along upper sidewalls of the first source/drain epitaxial structure and the second source/drain epitaxial structure as a protective spacer. The method further comprises forming a back-side dielectric cap in the back-side capping trench.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: February 14, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huan-Chieh Su, Cheng-Chi Chuang, Chih-Hao Wang, Zhi-Chang Lin, Li-Zhen Yu
  • SELF-ALIGNED AIR SPACERS AND METHODS FOR FORMING
    Publication number: 20230043669
    Abstract: A method of manufacturing an integrated circuit device including a self-aligned air spacer including the operations of forming a dummy gate, forming a sidewall on the dummy gate, forming a dummy layer on the sidewall, constructing a gate structure within an opening defined by the sidewall, removing at least a portion of the first dummy layer to form a first recess between the sidewall layer and the dummy gate, and capping the first recess to form a first air spacer.
    Type: Application
    Filed: August 5, 2021
    Publication date: February 9, 2023
    Inventors: Huan-Chieh SU, Jia-Chuan YOU, Cheng-Chi CHUANG, Chih-Hao WANG
  • SEMICONDUCTOR DEVICE HAVING A GATE CONTACT ON A LOW-K LINER
    Publication number: 20230039440
    Abstract: A device includes a substrate. A channel region of a transistor overlies the substrate and a source/drain region is in contact with the channel region. The source/drain region is adjacent to the channel region along a first direction. A source/drain contact is disposed on the source/drain region. A gate electrode is disposed on the channel region and a gate contact is disposed on the gate electrode. A first low-k dielectric layer is disposed between the gate contact and the source/drain contact along the first direction.
    Type: Application
    Filed: March 15, 2022
    Publication date: February 9, 2023
    Inventors: Meng-Huan JAO, Huan-Chieh SU, Yi-Bo LIAO, Cheng-Chi CHUANG, Jin CAI, Chih-Hao WANG
  • SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME
    Publication number: 20230034360
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a first gate stack wrapping around first nanostructures, a second gate stack wrapping around second nanostructures, a gate isolation structure interposing between the first gate stack and the second gate stack, a first source/drain feature adjoining the first nanostructures, a second source/drain feature adjoining the second nanostructures, and a source/drain spacer structure interposing between the first source/drain feature and the second source/drain feature. The gate isolation structure covers a sidewall of the source/drain spacer structure.
    Type: Application
    Filed: February 15, 2022
    Publication date: February 2, 2023
    Inventors: Huan-Chieh Su, Zhi-Chang Lin, Li-Zhen Yu, Chun-Yuan Chen, Lo-Heng Chang, Cheng-Chi Chuang, Chih-Hao Wang, Lin-Yu Huang
  • Semiconductor Devices with a Nitrided Capping Layer
    Publication number: 20230029002
    Abstract: The present disclosure describes a semiconductor device with a nitrided capping layer and methods for forming the same. One method includes forming a first conductive structure in a first dielectric layer on a substrate, depositing a second dielectric layer on the first conductive structure and the first dielectric layer, and forming an opening in the second dielectric layer to expose the first conductive structure and a portion of the first dielectric layer. The method further includes forming a nitrided layer on a top portion of the first conductive structure, a top portion of the portion of the first dielectric layer, sidewalls of the opening, and a top portion of the second dielectric layer, and forming a second conductive structure in the opening, where the second conductive structure is in contact with the nitrided layer.
    Type: Application
    Filed: January 18, 2022
    Publication date: January 26, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Chin Chang, Lin-Yu Huang, Shuen-Shin Liang, Sheng-Tsung Wang, Cheng-Chi Chuang, Chia-Hung Chu, Tzu Pei Chen, Yuting Cheng, Sung-Li Wang
  • Air spacer and capping structures in semiconductor devices
    Patent number: 11563001
    Abstract: A semiconductor device with air spacers and air caps and a method of fabricating the same are disclosed. The semiconductor device includes a substrate and a fin structure disposed on the substrate. The fin structure includes a first fin portion and a second fin portion. The semiconductor device further includes a source/drain (S/D) region disposed on the first fin portion, a contact structure disposed on the S/D region, a gate structure disposed on the second fin portion, an air spacer disposed between a sidewall of the gate structure and the contact structure, a cap seal disposed on the gate structure, and an air cap disposed between a top surface of the gate structure and the cap seal.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: January 24, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lin-Yu Huang, Chiao-Hao Chang, Cheng-Chi Chuang, Chih-Hao Wang, Ching-Wei Tsai, Kuan-Lun Cheng